Multi-chip module (MCM) with multi-port unified memory
A chiplet-based multi-chip module (MCM) comprises a package substrate that is separate from a base substrate. A first integrated circuit (IC) chiplet couples to the package substrate and comprises a first memory interface that transmits memory access information to carry out a memory operation. A first memory chiplet couples to the package substrate and comprises a logic base die and at least one memory die stacked on the logic base die. The logic base die comprises a first port to receive the memory access information from the first memory interface of the first IC chiplet, a second port to communicate with a third IC chiplet, a third port to communicate with the at least one memory die, and in-memory processing circuitry to control a transfer of the memory access information from the first port to the second port or the third port via a packet-switched protocol.
1 . A chiplet-based multi-chip module (MCM) to couple to a base substrate, the chiplet-based MCM comprising:
a package substrate that is separate from the base substrate;
a first integrated circuit (IC) chiplet coupled to the package substrate and comprising a first memory interface, the first memory interface to transmit memory access information sufficient to carry out a memory access operation; and
a second IC chiplet comprising a first memory chiplet coupled to the package substrate and comprising
a logic base die;
at least one memory die stacked on the logic base die, the at least one memory die comprising a memory space;
wherein the logic base die comprises a first port to receive the memory access information from the first memory interface of the first IC chiplet;
a second port to communicate with a third IC chiplet;
a third port to communicate with the at least one memory die; and
first in-memory processing circuitry to control a transfer of the memory access information from the first port to the second port or the third port via a packet-switched protocol.
2 . The chiplet-based MCM of claim 1 , wherein:
the first in-memory processing circuitry is configured to allow at least one of the first port or the second port access to any portion of the memory space via the third port.
3 . The chiplet-based MCM of claim 1 , wherein:
the first port comprises a first set of terminals positioned proximate a first edge of the first memory chiplet to couple to a first link, the first link comprising a first set of signal paths to connect the first IC chiplet to the first memory chiplet, the first set of terminals to receive the memory access information from the first IC chiplet that is sufficient to carry out the memory access operation.
4 . The chiplet-based MCM of claim 1 , wherein:
the second port comprises a second set of terminals positioned proximate a second edge of the first memory chiplet to couple to a second link, the second link comprising a second set of signal paths to connect the first memory chiplet to the third IC chiplet.
5 . The chiplet-based MCM of claim 1 , wherein:
the first memory chiplet comprises a high-bandwidth memory (HBM) chiplet.
6 . The chiplet-based MCM of claim 1 , wherein the first in-memory processing circuitry comprises:
coprocessing circuitry to perform a processing operation on data stored in the at least one memory die on behalf of the first IC chiplet.
7 . The chiplet-based MCM of claim 1 , wherein the first in-memory processing circuitry comprises:
first network-on-chip (NoC) circuitry.
8 . The chiplet-based MCM of claim 1 , further comprising:
the third IC chiplet, the third IC chiplet comprising a second memory chiplet comprising a fourth port coupled to the second port of the first memory chiplet, the second memory chiplet comprising second in-memory processing circuitry in communication with the first in-memory processing circuitry.
9 . The chiplet-based MCM of claim 8 , wherein:
the first in-memory processing circuitry comprises first NoC circuitry; and
the second in-memory processing circuitry comprises second NoC circuitry to communicate with the first NoC circuitry.
10 . The chiplet-based MCM of claim 9 , wherein the first IC chiplet further comprises:
third NoC circuitry coupled to the first memory interface to communicate with the first NoC circuitry and the second NoC circuitry.
11 . The chiplet-based MCM of claim 8 , wherein:
the first memory chiplet is configured to store first data consistent with a first memory hierarchy; and
wherein the second memory chiplet is configured to store second data consistent with a second memory hierarchy that is different than the first memory hierarchy.
12 . The chiplet-based MCM of claim 8 , wherein the first memory chiplet further comprises:
a fifth port coupled to the first in-memory processing circuitry to communicate with a fourth IC chiplet.
13 . The chiplet-based MCM of claim 12 , wherein the fourth IC chiplet comprises:
a third memory chiplet.
14 . The chiplet-based MCM of claim 1 , wherein:
the first IC chiplet comprises a first processing unit.
15 . The chiplet-based MCM of claim 14 , wherein:
the first processing unit comprises a first central processing unit (CPU) or a first graphics processing unit (GPU).
16 . A chiplet-based multi-chip module (MCM) to couple to a base substrate, the chiplet-based MCM comprising:
a package substrate that is separate from the base substrate;
a first integrated circuit (IC) chiplet coupled to the package substrate and comprising a first memory interface, the first memory interface to transmit memory access information sufficient to carry out a memory access operation;
a second IC chiplet coupled to the package substrate; and a first memory chiplet coupled to the package substrate and comprising
a logic base die;
at least one dynamic random access memory (DRAM) memory die stacked on the logic base die and comprising a memory space;
wherein the logic base die comprises first network-on-chip (NoC) circuitry to receive the memory access information, the first NoC circuitry to control transfer of the memory access information to the at least one dynamic random access memory (DRAM) memory die or the second IC chiplet via a packet-switched protocol.
17 . The chiplet-based MCM of claim 16 , wherein the first NoC circuitry includes:
coprocessing circuitry to perform a processing operation on data stored in the at least one DRAM memory die on behalf of the first IC chiplet.
18 . The chiplet-based MCM of claim 16 , wherein the first NoC circuitry comprises:
input buffer circuitry to receive the memory access information;
output buffer circuitry coupled to the at least one dynamic random access memory (DRAM) memory die and the second IC chiplet; and
crossbar switch circuitry to couple the input buffer circuitry to the at least one dynamic random access memory (DRAM) memory die or the second IC chiplet.
19 . The chiplet-based MCM of claim 16 , wherein:
the second IC chiplet comprises a second memory chiplet, the second memory chiplet including second NoC circuitry in communication with the first NoC circuitry.
20 . The chiplet-based MCM of claim 19 , wherein:
the first memory chiplet is configured to store first data consistent with a first memory hierarchy; and
wherein the second memory chiplet is configured to store second data consistent with a second memory hierarchy that is different than the first memory hierarchy.
21 . A method of operation in a chiplet-based multi-chip module (MCM), the chiplet-based MCM to couple to a base substrate, the chiplet-based MCM comprising a package substrate that is separate from the base substrate, a first integrated circuit (IC) chiplet coupled to the package substrate, and a first memory chiplet coupled to the package substrate and comprising a first port to connect to the first IC chiplet, a second port to connect to a second IC chiplet, memory with a memory space and network-on-chip (NoC) circuitry, the method comprising:
controlling a memory access transaction associated with the first port or the second port with the NoC circuitry that is compliant with a packet-switched protocol.
22 . The method of claim 21 , wherein controlling the memory access transaction associated with the first port or the second port with the NoC circuitry comprises:
performing a processing operation on data stored in the memory on behalf of the first IC chiplet.
23 . The method of claim 21 , wherein controlling the memory access transaction associated with the first port or the second port with the NoC circuitry comprises:
controlling a transfer between the first port and the second port via the packet-switched protocol.