Chiplet gearbox for low-cost multi-chip module applications
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a chiplet-based multi-chip module (MCM) is disclosed. The chiplet-based MCM includes a first integrated circuit (IC) chiplet comprising a first interface to receive a first set of information-carrying signals associated with a memory access operation. Conversion circuitry generates a second set of support signals associated with the memory access operation. The conversion circuitry aggregates the second set of support signals with the first set of information-carrying signals to generate an aggregate set of signals associated with the memory access operation. A second interface transmits the aggregate set of signals. Memory, comprising a memory interface coupled to the second interface of the first IC chiplet receives the aggregate set of signals.
1. A chiplet-based multi-chip module (MCM) to couple to a base substrate, comprising:
a first integrated circuit (IC) chiplet to couple to a package substrate that is separate from the base substrate, the first IC chiplet comprising
a first interface, the first interface to receive, from a second IC chiplet that is coupled to the package substrate, along a set of high speed links route along the package substrate, information-carrying signals transmitted from the second IC chiplet, the information-carrying signals associated with a memory access operation, the memory access operation carried out in response to a minimum set of signals comprising the information-carrying signals and non-information-carrying signals, the information-carrying signals excluding the non-information-carrying signals;
conversion circuitry to generate, on the first IC chiplet, the non-information-carrying signals, the conversion circuitry to merge the non-information-carrying signals with the information-carrying signals to generate a full set of signals that is compliant with the minimum set of signals to perform the memory access operation;
a second interface to transmit the full set of signals; and
memory, comprising a memory interface coupled to the second interface of the first IC chiplet to receive the full set of signals.
2. The chiplet-based MCM of claim 1 , wherein:
the non-information-carrying signals comprise at least one of a data bus inversion signal, a reference clock signal, a write enable signal, a write clock signal, a write strobe signal, or a read strobe signal.
3. The chiplet-based MCM of claim 1 , wherein:
the first IC chiplet comprises first circuitry that is formed in accordance with a first process node; and
the memory interface comprises second circuitry formed in accordance with a second process node that is slower than the first process node.
4. The chiplet-based MCM of claim 1 , wherein:
the first IC chiplet comprises a base die; and
the memory comprises a memory stack disposed on the base die.
5. The chiplet-based MCM of claim 4 , wherein:
the memory stack comprises a high-bandwidth memory (HBM) stack of dynamic random access memory (DRAM).
6. The chiplet-based MCM of claim 1 , wherein:
the first IC chiplet comprises a gearbox chiplet comprising a first input/output (I/O) width that is associated with the first interface, and a second I/O width that is associated with the second interface, the second I/O width being wider than the first I/O width; and
the memory comprises a memory chiplet coupled to the gearbox chiplet via a set of signaling links that corresponds to the second I/O width.
7. The chiplet-based MCM of claim 6 , wherein:
the memory chiplet comprises
a base die; and
a memory stack disposed on the base die.
8. The chiplet-based MCM of claim 7 , wherein:
the memory stack comprises a high-bandwidth memory (HBM) stack of dynamic random access memory (DRAM).
9. The chiplet-based MCM of claim 1 , wherein:
the first interface receives the information-carrying signals at a first signaling rate; and
the second interface transmits the full set of signals at a second signaling rate that is less than the first signaling rate.
10. The chiplet-based MCM of claim 9 , wherein:
the first signaling rate is an integer multiple faster than the second signaling rate.
11. An integrated circuit (IC) chiplet, comprising:
a first interface, the first interface to receive information-carrying signals transmitted from the second IC chiplet, the information-carrying signals associated with a memory access operation, the memory access operation carried out in response to a minimum set of signals comprising the information-carrying signals and non-information-carrying signals, the information-carrying signals excluding the non-information-carrying signals;
conversion circuitry to generate the non-information-carrying signals associated with the memory access operation, the conversion circuitry to merge the non-information-carrying signals with the information-carrying signals to generate a full set of signals that is compliant with the minimum set of signals to perform the memory access operation;
a second interface to transmit the full set of signals to a memory interface of a memory chiplet.
12. The IC chiplet of claim 11 , wherein:
the non-information-carrying signals comprise at least one of a data bus inversion signal, a reference clock signal, a write enable signal, a write clock signal, a write strobe signal, or a read strobe signal.
13. The IC chiplet of claim 11 , wherein:
the first interface, the conversion circuitry, and the second interface are formed in accordance with a first process node; and
the memory interface comprises second circuitry formed in accordance with a second process node that is slower than the first process node.
14. The IC chiplet of claim 11 , further comprising:
first input/output (I/O) circuitry of a first I/O width that is associated with the first interface; and
second I/O circuitry of a second I/O width that is associated with the second interface, the second I/O width being wider than the first I/O width.
15. The IC chiplet of claim 11 , wherein:
the first interface receives the information-carrying signals at a first signaling rate; and
wherein the second interface transmits the full set of signals at a second signaling rate that is less than the first signaling rate.
16. The IC chiplet of claim 15 , wherein:
the first signaling rate is an integer multiple faster than the second signaling rate.
17. A method of operation in an IC chiplet, comprising:
receiving, at a first interface, information-carrying signals associated with a memory access operation from a second IC chiplet, the memory access operation carried out in response to a minimum set of signals comprising the information-carrying signals and non-information-carrying signals, the information-carrying signals excluding the non-information-carrying signals;
generating, with conversion circuitry, the non-information-carrying signals associated with the memory access operation;
merging, with the conversion circuitry, the information-carrying signals with the information-carrying signals to form a full set of signals that is compliant with the minimum set of signals to perform the memory access operation; and
transmitting, with a second interface, the full set of signals to a memory interface.
18. The method of claim 17 , wherein:
the generating, with the conversion circuitry, the non-information-carrying signals comprises generating, with the conversion circuitry, at least one of a data bus inversion signal, a reference clock signal, a write enable signal, a write clock signal, a write strobe signal, or a read strobe signal.
19. The method of claim 17 , wherein:
the receiving, at the first interface, the information-carrying signals is carried out at a first signaling rate; and
the transmitting, with the second interface, the full set of signals is carried out at a second signaling rate that is less than the first signaling rate.
20. The method of claim 19 , wherein:
the first signaling rate is an integer multiple faster than the second signaling rate.