Universal memory interface utilizing die-to-die (D2D) interfaces between chiplets
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes memory control circuitry for controlling at least one memory die of a first memory type. A die-to-die (D2D) interface circuit couples to a host IC chiplet. The D2D interface circuit includes input/output (I/O) circuitry for coupling to multiple signaling lanes for transferring information packets with the host IC chiplet.
1. A chiplet-based multi-chip module (MCM), comprising:
a package substrate;
a host integrated circuit (IC) chiplet coupled to the package substrate and comprising:
at least one processing element;
a communications fabric switchably coupled to the at least one processing element; and
a primary die-to-die (D2D) interface to transfer memory information via a packet protocol from the at least one processing element via the communications fabric;
at least one memory chiplet comprising:
a secondary D2D interface coupled to the primary D2D interface via multiple signaling lanes;
a memory port comprising a memory physical interface of at least one first memory type for accessing memory storage of the at least one first memory type; and
wherein the multiple signaling lanes are configured to route information packets controlled by the communications fabric between the host IC chiplet and the at least one memory chiplet.
2. The chiplet-based MCM of claim 1 , wherein:
the communications fabric comprises a network-on-chip (NoC) circuit.
3. The chiplet-based MCM of claim 1 , wherein the multiple signaling lanes comprise:
multiple data lanes to route data packets.
4. The chiplet-based MCM of claim 3 , wherein the multiple data lanes comprise:
a first subset of data lanes to transfer first data for a first memory transaction during a first timing interval; and
a second subset of data lanes to transfer second data for a second memory transaction during the first timing interval.
5. The chiplet-based MCM of claim 4 , wherein during the first timing interval of operation:
the first subset of data lanes transfers write data for the first memory transaction; and
the second subset of data lanes transfers read data for the second memory transaction.
6. The chiplet-based MCM of claim 3 , wherein:
the multiple data lanes comprise half-duplex bidirectional data lanes.
7. The chiplet-based MCM of claim 3 , further comprising:
at least one control lane to route control packets controlled by the communications fabric between the host IC chiplet and the at least one memory chiplet.
8. The chiplet-based MCM of claim 7 , wherein the at least one control lane comprising:
an egress lane to transmit command and control information unidirectionally from the host IC chiplet to the at least one memory chiplet; and
an ingress lane to receive control information unidirectionally from the at least one memory chiplet to the host IC chiplet.
9. The chiplet-based MCM of claim 1 , further comprising:
at least one sideband link coupled between the host IC chiplet and the at least one memory chiplet.
10. The chiplet-based MCM of claim 1 , wherein:
the at least one memory chiplet further comprises a memory controller disposed between the secondary D2D interface and the memory port.
11. The chiplet-based MCM of claim 10 , wherein:
the secondary D2D interface, the memory port, and the memory controller of the at least one memory chiplet are formed in a base die; and
the memory storage comprises at least one memory die of the at least one first memory type stacked on the base die.
12. The chiplet-based MCM of claim 1 , wherein:
the memory storage of the at least one first memory type comprises high bandwidth memory (HBM), double-data rate (DDR) memory, low-power double-data rate (LPDDR) memory or graphics double-data rate (GDDR) memory.
13. A memory chiplet, comprising:
memory control circuitry for to control at least one memory die of a first memory type;
a die-to-die (D2D) interface circuit to couple to a host IC chiplet, the D2D interface circuit coupled to the memory control circuitry and comprising
input/output (I/O) circuitry to couple to multiple signaling lanes and to transfer information packets with the host IC chiplet.
14. The memory chiplet of claim 13 , further comprising:
a network-on-chip (NoC) circuit.
15. The memory chiplet of claim 13 , wherein the I/O circuitry comprises:
data I/O circuitry to couple to multiple data lanes.
16. The memory chiplet of claim 15 , wherein the data I/O circuitry comprises:
a first data I/O portion to transfer first data packets for a first memory transaction during a first timing interval; and
a second data I/O portion to transfer second data packets for a second memory transaction during the first timing interval.
17. The memory chiplet of claim 16 , wherein during the first timing interval:
the first data I/O portion receives write data for the first memory transaction; and
the second data I/O portion transmits read data for the second memory transaction.
18. The memory chiplet of claim 15 , wherein:
the data I/O circuitry comprises bidirectional data I/O circuitry.
19. The memory chiplet of claim 13 , wherein the I/O circuitry further comprises:
control I/O circuitry to couple to at least one control lane and to transfer control packets with the host IC chiplet.
20. The memory chiplet of claim 19 , wherein the control I/O circuitry comprising:
an egress I/O circuit to receive command and control information unidirectionally from the host IC chiplet to the memory chiplet; and
an ingress I/O circuit to transmit control information unidirectionally from the memory chiplet to the host IC chiplet.
21. The memory chiplet of claim 13 , further comprising:
at least one sideband I/O circuit to couple to a sideband link between the host IC chiplet and the memory chiplet.
22. The memory chiplet of claim 13 , wherein:
the memory control circuitry and the D2D interface circuit to couple to the host IC chiplet are formed in a base die; and
the at least one memory die of the first memory type is stacked on the base die.
23. The memory chiplet of claim 22 , wherein:
the at least one memory die comprises high bandwidth memory (HBM), double-data rate (DDR) memory, low-power double-data rate (LPDDR) memory or graphics double-data rate (GDDR) memory.
24. A host integrated circuit (IC) chiplet, comprising:
at least one processing element;
a communications fabric switchably coupled to the at least one processing element; and
a die-to-die (D2D) interface to transfer memory information from the at least one processing element via the communications fabric, the D2D interface circuit comprising
input/output (I/O) circuitry to couple to multiple signaling lanes and to transfer information packets to a memory chiplet.