Universal memory interface with dynamic bidirectional data transfers
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes at least one memory die of a first memory type. Memory control circuitry is coupled to the at least one memory die. An interface circuit is for coupling to a host IC chiplet. The interface circuit includes data input/output (I/O) circuitry for coupling to multiple data lanes. Link directional control circuitry selects, for a first memory transaction, a first subset of the multiple data lanes to transfer data between the memory chiplet and the host IC chiplet.
1. A chiplet-based multi-chip module (MCM) to couple to a base substrate, comprising:
a package substrate that is separate from the base substrate;
a host integrated circuit (IC) chiplet coupled to the package substrate and comprising:
at least one processing element;
a primary memory interface to transfer memory information from the at least one processing element via a communications fabric;
a memory chiplet comprising:
a secondary memory interface coupled to the primary memory interface via multiple data lanes;
a memory port comprising a memory physical interface to access memory storage; and
link directional control circuitry to select, for a first memory transaction, a first subset of the multiple data lanes to transfer data between the host IC chiplet and the memory chiplet.
2. The chiplet-based MCM of claim 1 , wherein the memory chiplet further comprises:
a read data pipeline; and
wherein the link directional control circuitry selects the first subset of the multiple data lanes based on usage information relating to the read data pipeline.
3. The chiplet-based MCM of claim 1 , wherein the memory chiplet further comprises:
a write data pipeline; and
wherein the link directional control circuitry selects the first subset of the multiple data lanes based on usage information relating to the write data pipeline.
4. The chiplet-based MCM of claim 3 , wherein:
the usage information relating to the write data pipeline comprises difference information between received write data requests and received write data corresponding to the received write data requests.
5. The chiplet-based MCM of claim 1 , wherein:
the link directional control circuitry is to select, for a memory write operation following a memory read operation, the first subset of the multiple data lanes to receive write data from the host IC chiplet.
6. The chiplet-based MCM of claim 1 , wherein:
the link directional control circuitry is to select, for a memory write operation performed concurrent with a memory read operation, a second subset of the multiple data lanes to receive write data from the host IC chiplet.
7. The chiplet-based MCM of claim 1 , wherein:
the multiple data lanes comprise multiple bidirectional data lanes.
8. The chiplet-based MCM of claim 1 , wherein:
the multiple data lanes corresponds to a full set of memory channels associated with the memory chiplet.
9. The chiplet-based MCM of claim 1 , wherein:
the secondary memory interface and the memory port of the memory chiplet are formed in a base die; and
the memory storage comprises at least one memory die stacked on the base die.
10. The chiplet-based MCM of claim 1 , wherein:
the memory storage comprises high bandwidth memory (HBM), double-data rate (DDR) memory, low-power double-data rate (LPDDR) memory or graphics double-data rate (GDDR) memory.
11. A memory chiplet, comprising:
at least one memory die;
memory control circuitry coupled to the at least one memory die;
an interface circuit comprising multiple input/output (I/O) circuits to couple to a host IC chiplet via multiple data lanes; and
link directional control circuitry to select, for a first memory transaction, a first subset of the multiple data lanes to transfer data between the memory chiplet and the host IC chiplet.
12. The memory chiplet of claim 11 , further comprising:
a read data pipeline; and
wherein the link directional control circuitry selects the first subset of the multiple data lanes based on usage information relating to the read data pipeline.
13. The memory chiplet of claim 11 , further comprising:
a write data pipeline; and
wherein the link directional control circuitry selects the first subset of the multiple data lanes based on usage information relating to the write data pipeline.
14. The memory chiplet of claim 13 , wherein:
the usage information relating to the write data pipeline comprises difference information between received write data requests and received write data.
15. The memory chiplet of claim 11 , wherein:
the link directional control circuitry is to select, for a memory write transaction following a memory read operation, the first subset of the multiple data lanes to receive write data from the host IC chiplet.
16. The memory chiplet of claim 11 , wherein:
the link directional control circuitry is to select, for a memory write operation performed concurrent with a memory read operation, a second subset of the multiple data lanes to receive write data from the host IC chiplet.
17. The memory chiplet of claim 11 , wherein:
the multiple I/O circuits comprise multiple bidirectional I/O circuits.
18. The memory chiplet of claim 11 , wherein:
the interface circuit and the memory control circuitry of the memory chiplet are formed in a base die; and
the at least one memory die is stacked on the base die.
19. The memory chiplet of claim 18 , wherein:
the at least one memory die comprises high bandwidth memory (HBM), double-data rate (DDR) memory, low-power double-data rate (LPDDR) memory or graphics double-data rate (GDDR) memory.
20. A host integrated circuit (IC) chiplet, comprising:
at least one processing element;
a communications fabric switchably coupled to the at least one processing element; and
a primary memory interface to transfer memory information from the at least one processing element via the communications fabric, the primary memory interface comprising
data input/output (I/O) circuitry to couple to a memory chiplet via multiple data lanes; and
link directional control circuitry responsive to control information from the memory chiplet to configure, for a first memory transaction, a first subset of the data I/O circuitry corresponding to a first subset of the multiple data lanes to transfer data between the host IC chiplet and the memory chiplet.