Method and apparatus to reduce complexity and cost for multi-chip modules (MCMs)
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a first integrated circuit (IC) chip device including a first substrate having traces that are of a first connection density and a first chiplet formed via a first IC manufacturing process and coupled to the primary substrate traces. The first IC chip device also includes a second chiplet formed via a second IC manufacturing process that is different than the first IC manufacturing process. The second chiplet includes a first interface that is coupled to the first chiplet via the traces of the primary substrate. The second chiplet also includes a second interface that exhibits a second connection density that is lower than the first connection density. A second IC chip device is coupled to the first IC chip device via the second interface of the second chiplet. A second substrate is provided for mounting the first IC chip device and the second IC chip device.
1 . A multi-chip module (MCM), comprising:
a first integrated circuit (IC) chip device comprising,
a first substrate comprising traces that are of a first connection density;
a first chiplet formed via a first IC manufacturing process and coupled to the traces of the first substrate;
a second chiplet formed via a second IC manufacturing process that is different than the first IC manufacturing process, the second chiplet comprising a first interface that is coupled to the first chiplet via the traces of the first substrate, the second chiplet comprising a second interface that exhibits a second connection density that is lower than the first connection density;
a second IC chip device coupled to the first IC chip device via the second interface of the second chiplet; and
a second substrate, the first IC chip device being mounted to the second substrate, the second IC chip device being mounted to the second substrate.
2 . The MCM of claim 1 , wherein the first substrate comprises:
a mold material comprising redistribution layer (RDL) paths to interconnect the first chiplet to the second chiplet in accordance with a wafer level fanout (WLFO) process, or a silicon interposer, or an organic interposer.
3 . The MCM of claim 1 , wherein the second substrate comprises:
an organic substrate, or a silicon substrate.
4 . The MCM of claim 1 , wherein:
the first IC manufacturing process comprises a memory device process; and
the second IC manufacturing process comprises a logic device process.
5 . The MCM of claim 1 , further comprising:
external interface circuitry comprising a first number of signaling paths to communicate with at least one IC die stacked with the first IC chip device.
6 . The MCM of claim 5 , wherein:
the external interface circuitry comprises through-silicon-vias (TSVs) formed in the first chiplet that correspond at least to the first number of signaling paths.
7 . The MCM of claim 6 , wherein:
the first chiplet comprises:
a primary interface to couple to the first number of signaling paths of the TSVs;
a secondary interface to couple to the first substrate, the secondary interface comprising a second number of signaling paths that is less than the first number of signaling paths; and
a first multiplexing/demultiplexing circuit to transfer signals between the primary interface and the secondary interface.
8 . The MCM of claim 5 , wherein:
the external interface circuitry comprises through-silicon-vias (TSVs) formed in the second chiplet that correspond at least to the first number of signaling paths.
9 . The MCM of claim 1 , wherein:
the first integrated circuit (IC) chip device comprises a logic base chip device for a stacked memory device; and
the second IC chip device comprises a computer processing unit (CPU) or graphics processing unit (GPU).
10 . A memory device, comprising:
a logic integrated circuit (IC) chip device comprising:
a first substrate comprising traces that are of a first connection density;
a first chiplet formed via a first IC manufacturing process and coupled to the traces of the first substrate;
a second chiplet formed via a second IC manufacturing process that is different than the first IC manufacturing process, the second chiplet comprising a first interface that is coupled to the first chiplet via the traces of the first substrate, the second chiplet comprising a second interface that exhibits a second connection density that is lower than the first connection density;
at least one memory IC die stacked with the logic IC chip device; and
external interface circuitry comprising a first number of signaling paths for the at least one memory IC die to communicate with the logic IC chip device.
11 . The memory device of claim 10 , wherein the first substrate comprises:
a mold material comprising redistribution layer (RDL) paths to interconnect the first chiplet to the second chiplet in accordance with a wafer level fanout (WLFO) process, or a silicon interposer, or an organic interposer.
12 . The memory device of claim 10 , wherein:
the first IC manufacturing process comprises a memory device process; and
the second IC manufacturing process comprises a logic device process.
13 . The memory device of claim 10 , wherein:
the external interface circuitry comprises through-silicon-vias (TSVs) formed in the first chiplet that correspond at least to the first number of signaling paths.
14 . The memory device of claim 13 , wherein the first chiplet comprises:
a primary interface to couple to the first number of signaling paths of the TSVs;
a secondary interface to couple to the first substrate, the secondary interface comprising a second number of signaling paths that is less than the first number of signaling paths; and
a first multiplexing/demultiplexing circuit to transfer signals between the primary interface and the secondary interface.
15 . The memory device of claim 10 , wherein:
the external interface circuitry comprises through-silicon-vias (TSVs) formed in the second chiplet that correspond at least to the first number of signaling paths.
16 . An integrated circuit (IC) chip device, comprising:
a first substrate to mount to a main substrate, the first substrate comprising traces that are of a first connection density;
a first chiplet formed via a first IC manufacturing process and coupled to the traces of the first substrate;
a second chiplet formed via a second IC manufacturing process that is different than the first IC manufacturing process, the second chiplet comprising a first interface that is coupled to the first chiplet via the traces of the first substrate, the second chiplet comprising a second interface that exhibits a second connection density that is lower than the first connection density, the second interface to couple to a second IC chip device that is mounted to th main substrate; and
external interface circuitry comprising a first number of signaling paths for the IC chip device to communicate with the second IC chip device.
17 . The IC chip device of claim 16 , wherein the first substrate comprises:
a mold material comprising redistribution layer (RDL) paths to interconnect the first chiplet to the second chiplet in accordance with a wafer level fanout (WLFO) process, or a silicon interposer, or an organic interposer.
18 . The IC chip device of claim 16 , wherein:
the first IC manufacturing process comprises a memory device process; and
the second IC manufacturing process comprises a logic device process.
19 . The IC chip device of claim 16 , wherein:
the external interface circuitry comprises through-silicon-vias (TSVs) formed in the first chiplet that correspond at least to the first number of signaling paths.
20 . The IC chip device of claim 19 , wherein the first chiplet comprises:
a primary interface to couple to the first number of signaling paths of the TSVs;
a secondary interface to couple to the first substrate, the secondary interface comprising a second number of signaling paths that is less than the first number of signaling paths; and
a first multiplexing/demultiplexing circuit to transfer signals between the primary interface and the secondary interface.
21 . The IC chip device of claim 16 , wherein:
the external interface circuitry comprises through-silicon-vias (TSVs) formed in the second chiplet that correspond at least to the first number of signaling paths.