Reconstructed substrates for high I/O counts application and methods for forming the same

1 . A package assembly comprising:

a package substrate comprising a molding material layer and a plurality of substrate portions embedded in the molding material layer, wherein the plurality of substrate portions comprises a plurality of metal bonding pads and a bottom surface of the plurality of metal bonding pads is substantially co-planar with a bottom surface of the molding material layer;

a redistribution layer (RDL) structure on the package substrate, wherein an outer sidewall of the RDL structure is substantially aligned with an outer sidewall of the molding material layer;

a plurality of semiconductor devices on the RDL structure; and

a ball grid array contacting the bottom surface of the metal bonding pads.

2 . The package assembly of claim 1 , wherein the plurality of substrate portions are substantially aligned in a longitudinal direction.

3 . The package assembly of claim 2 , wherein the plurality of semiconductor devices comprises a system on chip (SOC) device and a plurality of high bandwidth memory (HBM) devices.

4 . The package assembly of claim 3 , wherein the SOC device bridges the plurality of substrate portions and the plurality of HBM devices are located on opposing ends of the SOC device in the longitudinal direction.

5 . The package assembly of claim 1 , wherein the molding material layer comprises an epoxy molding compound (EMC).

6 . The package assembly of claim 1 , wherein the molding material layer comprises an outer molding material layer portion that is formed around a perimeter of the plurality of substrate portions.

7 . The package assembly of claim 6 , wherein the molding material layer further comprises a central molding material layer portion that is formed between the plurality of substrate portions and connects opposing sides of the outer molding material layer portion.

8 . The package assembly of claim 7 , wherein the central molding material layer portion has a width in a range from 0.5 mm to 5.0 mm and the outer molding material layer portion has a width in a range from 0.05 mm to 1.0 mm.

9 . The package assembly of claim 1 , wherein the molding material layer is bonded to a bottom surface of the RDL structure.

10 . The package assembly of claim 1 , further comprising a plurality of bump structures that connect the RDL structure to the plurality of substrate portions.

11 . The package assembly of claim 10 , further comprising an underfill layer between the RDL structure and the plurality of substrate portions, and around the plurality of bump structures.

12 . The package assembly of claim 1 , wherein the RDL structure comprises a first RDL layer contacting an upper surface of the package substrate and including a plurality of metal RDL vias that electrically connect the RDL structure to the package substrate.

13 . The package assembly of claim 12 , wherein the package substrate comprises a plurality of package substrate upper bonding pads on the upper surface of the package substrate, and the plurality of metal RDL vias contact the plurality of package substrate upper bonding pads, respectively.

14 . A package assembly comprising:

a re-constructed package substrate comprising:

a plurality of substrate sections that are substantially aligned in a lengthwise direction; and

a molding material layer comprising:

an outer molding material layer portion that is formed around an entire perimeter of the plurality of substrate sections in a plan view; and

a central molding material layer portion that is formed between the plurality of substrate sections and connects opposing sides of the outer molding material layer portion in the plan view; and

a redistribution layer (RDL) structure on the re-constructed package substrate; and

a plurality of semiconductor devices that are flip chip bonded on the RDL structure, the plurality of semiconductor devices comprising:

a system on chip (SOC) device that bridges the plurality of substrate sections; and

a plurality of high bandwidth memory (HBM) devices located on opposing ends of the SOC device in the longitudinal direction.

15 . A package structure comprising:

a reconstructed substrate including a molding material layer and a plurality of substrate sections in the molding material layer, wherein the plurality of substrate sections comprises:

a dielectric layer having a bottom surface substantially aligned with a bottom surface of the molding material layer; and

a plurality of metal bonding pads in the dielectric layer and having a bottom surface substantially co-planar with the bottom surface of the dielectric layer and the bottom surface of the molding material layer;

a redistribution layer (RDL) structure on the reconstructed substrate, wherein an outer sidewall of the RDL structure is substantially aligned with an outer sidewall of the molding material layer;

a plurality of semiconductor dies on the RDL structure; and

a ball grid array contacting the bottom surface of the plurality of metal bonding pads.

16 . The package structure of claim 15 , wherein the RDL structure comprises a plurality of dielectric layers and a plurality of metal layers in the plurality of dielectric layers.

17 . The package structure of claim 16 , wherein the RDL structure further comprises a plurality of metal vias connecting the plurality of metal layers.

18 . The package structure of claim 17 , further comprising:

a plurality of bump structures connecting the RDL structure to the plurality of substrate sections; and

an underfill layer around the plurality of bump structures, wherein the molding material layer is around the underfill layer.

19 . The package structure of claim 16 , wherein the plurality of substrate sections comprises a plurality of cored substrate sections.

20 . The package structure of claim 15 , wherein a semiconductor die of the plurality of semiconductor dies is electrically coupled to the plurality of substrate sections.