Dielectric walls for complementary field effect transistors
View Patent ↗In an embodiment, a device includes: a dielectric wall; nanostructures abutting the dielectric wall; a lower source/drain region adjoining a lower subset of the nanostructures; an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region; and a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall.
1. A device comprising:
a dielectric wall;
nanostructures abutting the dielectric wall;
a lower source/drain region adjoining a lower subset of the nanostructures;
an upper source/drain region adjoining an upper subset of the nanostructures, the upper source/drain region oppositely doped from the lower source/drain region;
a shared source/drain contact contacting the upper source/drain region and the lower source/drain region, the shared source/drain contact extending into the dielectric wall; and
an inter-layer dielectric on the upper source/drain region, the shared source/drain contact extending through the inter-layer dielectric, the shared source/drain contact having an upper portion in the inter-layer dielectric and having a lower portion in the dielectric wall, the lower portion of the shared source/drain contact being taller than the upper portion of the shared source/drain contact.
2. The device of claim 1 , wherein the lower source/drain region is a p-type source/drain region and the upper source/drain region is an n-type source/drain region.
3. The device of claim 1 , wherein the lower source/drain region is an n-type source/drain region and the upper source/drain region is a p-type source/drain region.
4. The device of claim 1 , wherein the upper portion of the shared source/drain contact is wider than the lower portion of the shared source/drain contact.
5. The device of claim 1 further comprising:
an isolation region on a substrate, the nanostructures protruding from the isolation region, the dielectric wall contacting a top surface of the isolation region.
6. The device of claim 1 further comprising:
an isolation region on a substrate, the nanostructures protruding from the isolation region, the dielectric wall contacting a top surface of the substrate.
7. A device comprising:
a dielectric wall;
first nanostructures contacting a sidewall of the dielectric wall;
second nanostructures above the first nanostructures and contacting the sidewall of the dielectric wall, the second nanostructures oppositely doped from the first nanostructures;
a gate structure extending along top surfaces and sidewalls of the second nanostructures, along top surfaces and sidewalls of the first nanostructures, and along a top surface and a sidewall of the dielectric wall; and
a lower source/drain region adjoining the first nanostructures, the dielectric wall having a first portion adjacent the lower source/drain region, the dielectric wall having a second portion beneath the gate structure, the second portion of the dielectric wall having a greater height than the first portion of the dielectric wall.
8. The device of claim 7 , wherein a top surface of the gate structure is above a top surface of the dielectric wall.
9. The device of claim 7 , wherein a top surface of the gate structure is coplanar with a top surface of the dielectric wall.
10. The device of claim 7 , wherein the dielectric wall is single-layered.
11. The device of claim 7 , wherein the dielectric wall is multi-layered.
12. The device of claim 7 , wherein the lower source/drain region is a lower source region, and the device further comprises:
a lower drain region, the first nanostructures disposed between the lower drain region and the lower source region;
an upper source region;
an upper drain region, the second nanostructures disposed between the upper drain region and the upper source region;
a shared source/drain contact contacting the upper drain region and the lower drain region;
a lower source/drain contact contacting a back-side of the lower source region; and
an upper source/drain contact contacting a front-side of the upper source region.
13. A method comprising:
forming a dielectric wall abutting nanostructures, wherein forming the dielectric wall comprises:
forming a plurality of dielectric walls, the nanostructures disposed between the dielectric walls; and
removing a subset of the dielectric walls;
etching a source/drain recess in the nanostructures;
growing a lower source/drain region in the source/drain recess;
growing an upper source/drain region over the lower source/drain region in the source/drain recess;
depositing an inter-layer dielectric on the upper source/drain region;
patterning a contact opening extending through the inter-layer dielectric and into the dielectric wall, the contact opening exposing the upper source/drain region and the lower source/drain region; and
forming a source/drain contact in the contact opening.
14. The method of claim 13 , wherein patterning the contact opening comprises:
performing a first etch to form an upper portion of the contact opening in the inter-layer dielectric, the upper portion of the contact opening exposing a top surface of the upper source/drain region; and
performing a second etch to form a lower portion of the contact opening in the dielectric wall, the lower portion of the contact opening exposing a sidewall of the upper source/drain region and a sidewall of the lower source/drain region.
15. The method of claim 13 further comprising:
after forming the dielectric wall, forming an isolation region, the nanostructures protruding from the isolation region.
16. The method of claim 13 further comprising:
before forming the dielectric wall, forming an isolation region, the nanostructures protruding from the isolation region.
17. The method of claim 13 , wherein the contact opening has an upper portion in the inter-layer dielectric and has a lower portion in the dielectric wall, the upper portion of the contact opening being wider than the lower portion of the contact opening.
18. The method of claim 13 , wherein the contact opening has an upper portion in the inter-layer dielectric and has a lower portion in the dielectric wall, the lower portion of the contact opening being taller than the upper portion of the contact opening.
19. The method of claim 13 , further comprising:
forming a gate structure around the nanostructures, the dielectric wall having a first portion adjacent the lower source/drain region, the dielectric wall having a second portion beneath the gate structure, the second portion of the dielectric wall having a greater height than the first portion of the dielectric wall.
20. The method of claim 13 , further comprising:
forming a gate structure around the nanostructures, the dielectric wall having a first portion adjacent the lower source/drain region, the dielectric wall having a second portion beneath the gate structure, the second portion of the dielectric wall having a same height as the first portion of the dielectric wall.