Lateral capacitors of semiconductor devices
A semiconductor device is provided. The semiconductor device includes a substrate, a gate electrode, an isolation structure, and an electrode plate. The gate electrode is over the substrate and the isolation structure is in contact with the gate electrode. The electrode plate is in the isolation structure.
1 . A semiconductor device for a lateral capacitor, comprising:
a substrate;
a gate electrode over the substrate;
an isolation structure comprising:
a dielectric core having laterally opposite side surfaces; and
a dielectric liner laterally surrounding the dielectric core, wherein at least a portion of the dielectric liner is in direct physical contact with a sidewall of the gate electrode; and
an electrode plate within the isolation structure, wherein the electrode plate is between the dielectric liner and the dielectric core.
2 . The semiconductor device of claim 1 , wherein the electrode plate extends vertically along the isolation structure.
3 . The semiconductor device of claim 2 , wherein the substrate has an upper substrate surface, and the electrode plate has a first portion over the upper substrate surface and a second portion under the upper substrate surface.
4 . The semiconductor device of claim 1 , wherein the electrode plate is laterally spaced apart from the gate electrode by the dielectric liner.
5 . The semiconductor device of claim 1 , wherein a portion of the dielectric core is under the electrode plate.
6 . The semiconductor device of claim 1 , further comprising:
a dielectric layer over the gate electrode, the dielectric layer has an upper dielectric surface and the electrode plate has an upper surface substantially coplanar with the upper dielectric surface.
7 . The semiconductor device of claim 6 , further comprising:
a contact structure in the dielectric layer, the contact structure having an upper surface substantially coplanar with the upper surface of the electrode plate.
8 . The semiconductor device of claim 1 , wherein the gate electrode is a first gate electrode and the electrode plate is a first electrode plate, further comprising:
a second gate electrode over the substrate, the second gate electrode is laterally adjacent to the first gate electrode, and
the isolation structure is in contact with the first gate electrode and the second gate electrode; and
a second electrode plate in the isolation structure spaced apart from the first electrode plate, wherein the first electrode plate and the second electrode plate are between the dielectric liner and the dielectric core.
9 . The semiconductor device of claim 8 , wherein the first electrode plate is spaced apart from the second electrode plate by the dielectric core.
10 . The semiconductor device of claim 9 , wherein the dielectric core has a first width extending between opposite side surfaces contacting the dielectric liner and a second width extending between opposite side surfaces contacting the first electrode plate and the second electrode plate, and the second width is narrower than the first width.
11 . The semiconductor device of claim 9 , wherein the first electrode plate is on a portion of the dielectric liner, and the portion of the dielectric liner is at least in contact with the first gate electrode.
12 . The semiconductor device of claim 8 , wherein the first electrode plate has a side surface area, the first gate electrode has a side surface area, and the side surface area of the first electrode plate is at least as large as the side surface area of the first gate electrode.
13 . The semiconductor device of claim 8 , wherein the second electrode plate has an upper portion over the substrate and a lower portion in the substrate.
14 . A method of forming a semiconductor device for a lateral capacitor, comprising:
forming a layer of gate electrode material over a substrate;
forming a trench through the layer of gate electrode material partially into the substrate, the trench divides the layer of gate electrode material into a first gate electrode and a second gate electrode at laterally adjacent sides thereof;
forming an isolation structure within the trench, wherein forming the isolation structure comprises:
a dielectric core having laterally opposite side surfaces; and
a dielectric liner laterally surrounding the dielectric core, wherein at least a portion of the dielectric liner is in direct physical contact with a sidewall of the gate electrode; and
forming an electrode plate in the isolation structure, wherein the electrode plate is between the dielectric liner and the dielectric core.
15 . The method of claim 14 , wherein forming the isolation structure comprises:
forming a first dielectric material to partially fill the trench, the first dielectric material is conformal to the trench and in contact with the first gate electrode and the second gate electrode;
forming a second dielectric material to at least fill the trench, the second dielectric material is different from the first dielectric material; and
performing a planarization technique to form the isolation structure in the trench, the dielectric liner is formed from the first dielectric material and the dielectric core is formed from the second dielectric material.
16 . The method of claim 15 , wherein forming the electrode plate comprises:
recessing the dielectric core to form an opening in the isolation structure, a portion of the dielectric liner is exposed in the opening to define lateral boundaries of the opening;
depositing an electrode material in the opening, the electrode material is conformal to the opening; and
removing a portion of the electrode material to leave a portion thereof on the dielectric liner.
17 . The semiconductor device of claim 8 , further comprising:
a first dielectric layer in the isolation structure laterally between the first electrode plate and the dielectric core; and
a second dielectric layer in the isolation structure laterally adjacent to the first dielectric layer, wherein the second dielectric layer is laterally between the second electrode plate and the dielectric core, and the first dielectric layer is spaced apart from the second dielectric layer by the dielectric core.