IP Library › Granted Patent US 12,660,696
Granted Patent B2
US 12,660,696 · App. 18/152,453 · Granted Jun 16, 2026

Integrated circuit packages and methods of forming the same

Inventors: Tsung-Yuan Yu (Taipei, TW); Tzuan-Horng Liu (Longtan Township, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10W90/00H10P54/00H10W20/20H10W70/611H10W70/65H10W70/685H10W74/012H10W74/019H10W74/117H10W74/15H10W72/072H10W72/073H10W90/722H10W90/724H10W90/734
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Quick Facts
Patent No.
US 12,660,696
App. No.
18/152,453
Granted
Jun 16, 2026
Kind
B2
Abstract

Embodiments include a stacked semiconductor device and methods of forming the same. The stacked semiconductor device includes a first package embedded in a second package. Forming the first package includes mounting a first integrated circuit device to a first workpiece by a first set of solder connectors, depositing a first underfill between the first integrated circuit device and the first workpiece, and forming a first encapsulant laterally surrounding the first integrated circuit device. The first package is mounted to a second workpiece by a second set of solder connectors, a second underfill is deposited between the first package and the second workpiece, and a second encapsulant is deposited to laterally surround the first package.

Claims (68)

1 . A method comprising:

forming a first package, comprising:

mounting a first integrated circuit device to a first workpiece by a first set of connectors,

depositing a first underfill between the first integrated circuit device and the first workpiece;

forming a first encapsulant laterally surrounding the first integrated circuit device, and

separating the first package, the first package including the first integrated circuit device and a first portion of the first workpiece;

mounting the first package to a second workpiece by a second set of connectors, the second workpiece including an interconnect structure;

depositing a second underfill between the first package and the second workpiece, wherein the second underfill extends up sidewalls of the first package;

forming a second encapsulant laterally surrounding the first package, wherein the second underfill is interposed between the first encapsulant and the second encapsulant; and

separating a second package from the second workpiece, the second package including the first package and a second portion of the second workpiece.

2 . The method of claim 1 , further comprising:

prior to separating the second package, flipping over the second workpiece;

forming first conductive connectors at a front side of the second workpiece; and

forming a third set of connectors on a front side of the second workpiece on the first conductive connectors.

3 . The method of claim 2 , further comprising:

forming second conductive connectors at the front side of the second workpiece, the second conductive connectors smaller than the first conductive connectors; and

mounting a first integrated package device to the second conductive connectors.

4 . The method of claim 1 , further comprising:

preparing the first workpiece, comprising:

forming the second set of connectors on a front side of the first workpiece,

securing the first workpiece to a handling apparatus,

thinning a backside of the first workpiece to reveal a set of through-vias,

forming a polymer layer over the backside of the first workpiece, and

forming first conductive connectors through the polymer layer to contact the set of through-vias; and

mounting the first integrated circuit device to the first workpiece by the first set of connectors on the first conductive connectors.

5 . The method of claim 4 , wherein after mounting the first integrated circuit device, one of the first conductive connectors is free from solder.

6 . The method of claim 1 , wherein the first integrated circuit device is mounted to a front side of the first workpiece.

7 . The method of claim 1 , further comprising:

mounting a second structure to the second workpiece adjacent the first package; and

forming the second encapsulant to laterally surround the second structure.

8 . The method of claim 7 , wherein the second structure is a second integrated circuit die, the second encapsulant extending over an upper surface of the second structure.

9 . The method of claim 1 , further comprising:

mounting the second package to a substrate;

mounting a second integrated circuit die to the substrate adjacent the second package; and

depositing a third underfill between the second package and the substrate and a fourth underfill between the second integrated circuit die and the substrate.

10 . A method comprising:

depositing a passivation layer over a first workpiece;

forming a first set of connectors through the passivation layer, the first set of connectors electrically coupled to a first interconnect of the first workpiece;

attaching a first device die to the first set of connectors by corresponding first connectors;

encapsulating the first device die in a first encapsulant;

forming a second set of connectors on the first workpiece opposite the first set of connectors;

singulating a first package from the first workpiece, the first package including the first device die;

attaching the second set of connectors of the first package to a second workpiece by corresponding second connectors;

depositing an underfill between the first device die and the second workpiece, wherein the underfill extends along sidewalls of the first encapsulant;

encapsulating the first package in a second encapsulant;

forming a third set of connectors on the second workpiece on a side of the second workpiece opposite the first package; and

singulating a second package from the second workpiece, the second package including the first package.

11 . The method of claim 10 , wherein the passivation layer is a first passivation layer, further comprising:

thinning a backside of the first workpiece, the backside of the first workpiece opposite the first passivation layer, the thinning exposing a set of through-vias extending through the first workpiece to contact the first interconnect;

depositing a second passivation layer on the backside of the first workpiece; and

forming the second set of connectors on the second passivation layer, the second set of connectors electrically coupled to the set of through-vias.

12 . The method of claim 10 , wherein a first subset of the first set of connectors remains unbonded after attaching the first device die, wherein the first encapsulant covers and laterally surrounds the first subset of the first set of connectors.

13 . The method of claim 10 , further comprising attaching a second device die to the second workpiece by corresponding third connectors, the second device die being shorter than the first package, wherein the second encapsulant also encapsulates the second device die.

14 . A method comprising:

attaching a first die to a first surface of a second die with a first set of connectors, the second die being part of a first workpiece;

forming a first underfill between the first die and the second die;

forming a first encapsulant on the first surface of the second die and along sidewalls of the first die;

singulating to separate the second die from the first workpiece;

attaching the second die to a first surface of a second workpiece with a second set of connectors;

forming a second underfill between the second die and the second workpiece;

forming a second encapsulant on the first surface of the second workpiece, the second encapsulant extending along sidewalls of the first encapsulant; and

singulating the second workpiece to form a packaged device.

15 . The method of claim 14 , wherein the second underfill contacts the sidewalls of the first encapsulant.

16 . The method of claim 14 , wherein a sidewall of the first encapsulant is aligned with a sidewall of the second die.

17 . The method of claim 14 , wherein the second workpiece is a redistribution structure.

18 . The method of claim 17 , wherein the first die is attached to the second die such that a face of the first die is bonded to a face of the second die.

19 . The method of claim 1 , wherein the first set of connectors comprises solder connectors.

20 . The method of claim 10 , further comprising attaching a surface mount device to the second workpiece on the side of the second workpiece opposite the first package.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2023
From: YU, TSUNG-YUAN; LIU, TZUAN-HORNG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 062331/0568 →
Continuity (1)
Related Publication 20240234400A1 · Jul 11, 2024
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