Cell having stacked pick-up region
View Patent ↗An integrated circuit includes a p-type active zone located in an n-type well, an n-type active zone located in a p-type well, an n-type pick-up region located in the n-type well, and a p-type pick-up region located in the p-type well. The integrated circuit also includes a first power rail and a second power rail extending in a first direction, and a first conductive segment and a second conductive segment extending in a second direction. The first power rail, the p-type active zone, the n-type active zone, and the second power rail are arranged along the second direction separating from each other. The first conductive segment connects the n-type pick-up region with the first power rail, and the second conductive segment connects the p-type pick-up region with the second power rail.
1. An integrated circuit comprising:
two parallel active zones extending in a first direction, including a p-type active zone located in an n-type well and an n-type active zone located in a p-type well, wherein each of the p-type active zone and the n-type active zone includes a channel region between a source or a drain aligned along the first direction, and wherein the p-type active zone having channel regions is separated from the n-type active zone having channel regions along a second direction that is different from the first direction;
an n-type pick-up region located in the n-type well, wherein an n-type dopant concentration of the n-type pick-up region is higher than an n-type dopant concentration of the n-type well;
a p-type pick-up region located in the p-type well, wherein a p-type dopant concentration of the p-type pick-up region is higher than a p-type dopant concentration of the p-type well;
a first power rail and a second power rail extending in the first direction, wherein the first power rail, the p-type active zone, the n-type active zone, and the second power rail are arranged along the second direction such that the p-type active zone is between the first power rail and the n-type active zone while the n-type active zone is between the p-type active zone and the second power rail; and
a first conductive segment and a second conductive segment extending in the second direction, wherein the n-type pick-up region is conductively connected to the first power rail with the first conductive segment, and the p-type pick-up region is conductively connected to the second power rail with the second conductive segment;
a first gate-strip and a second gate-strip extending in the second direction, wherein the first gate-strip overlaps the n-type pick-up region and the second gate-strip overlaps the p-type pick-up region;
a first dummy gate extending in the second direction over the p-type active zone; and
a second dummy gate extending in the second direction over the n-type active zone.
2. The integrated circuit of claim 1 , wherein the n-type pick-up region is between the first power rail and the p-type active zone and separates the first power rail from the p-type active zone.
3. The integrated circuit of claim 1 , wherein the p-type pick-up region is between the second power rail and the n-type active zone and separates the second power rail from the n-type active zone.
4. The integrated circuit of claim 1 , wherein the n-type pick-up region is separated from the p-type pick-up region by the two parallel active zones.
5. The integrated circuit of claim 1 , further comprising:
a via connection connected between the first power rail and the first conductive segment.
6. The integrated circuit of claim 1 , further comprising:
a via connection connected between the second power rail and the second conductive segment.
7. The integrated circuit of claim 1 , wherein the n-type pick-up region has a width extending in the first direction and has a height extending in the second direction, and wherein the height is less than 25% of the width.
8. The integrated circuit of claim 1 , wherein the p-type pick-up region has a width extending in the first direction and has a height extending in the second direction, and wherein the height is less than 25% of the width.
9. The integrated circuit of claim 1 , wherein the p-type well is a part of a p-type substrate and the n-type well is formed in the p-type substrate.
10. The integrated circuit of claim 1 , wherein the n-type well is a part of a n-type substrate and the p-type well is formed in the n-type substrate.
11. The integrated circuit of claim 1 , further comprising:
an analog cell including a circuit having transistors in the p-type active zone and the n-type active zone.
12. The integrated circuit of claim 1 , wherein:
the first gate-strip is aligned with the first dummy gate along the second direction; and
the second gate-strip is aligned with the second dummy gate along the second direction.
13. The integrated circuit of claim 1 , wherein:
the first gate-strip, the second gate-strip, the first dummy gate, the second dummy gate, the first conductive segment, and the second conductive segment are all at a same vertical level.
14. The integrated circuit of claim 1 , wherein:
the first gate-strip and the second gate-strip are configured to be electrically floating.
15. An integrated circuit comprising:
two parallel active zones extending in a first direction, including a first-type active zone located in a second-type well and a second-type active zone located in a first-type well, wherein each of the first-type active zone and the second-type active zone includes a channel region between a source or a drain aligned along the first direction, and wherein the first-type active zone having channel regions is separated from the second-type active zone having channel regions along a second direction that is different from the first direction;
a second-type pick-up region located in the second-type well, wherein a second-type dopant concentration of the second-type pick-up region is higher than a second-type dopant concentration of the second-type well;
a first-type pick-up region located in the first-type well, wherein a first-type dopant concentration of the first-type pick-up region is higher than a first-type dopant concentration of the first-type well;
a first power rail and a second power rail extending in the first direction, wherein the first power rail, the first-type active zone, the second-type active zone, and the second power rail are arranged along the second direction such that the first-type active zone is between the first power rail and the second-type active zone while the second-type active zone is between the first-type active zone and the second power rail;
a first conductive segment extending in the second direction, wherein the second-type pick-up region is conductively connected to the first power rail with the first conductive segment;
an analog cell including a circuit having transistors in the first-type active zone and the second-type active zone; and
a first dummy gate extending in the second direction over the first-type active zone; and
a second dummy gate extending in the second direction over the second-type active zone.
16. The integrated circuit of claim 15 , further comprising:
a second conductive segment extending in the second direction, wherein and the first-type pick-up region is conductively connected to the second power rail with the second conductive segment.
17. The integrated circuit of claim 16 , wherein the first-type well is n-type and the second-type well is p-type, wherein the first power rail is configured to have a first supply voltage and the second power rail is configured to have a second supply voltage, and wherein the second supply voltage is lower than the first supply voltage.
18. The integrated circuit of claim 16 , wherein the first-type well is p-type and the second-type well is n-type, wherein the first power rail is configured to have a second supply voltage and the second power rail is configured to have a first supply voltage, and wherein the second supply voltage is lower than the first supply voltage.
19. An integrated circuit comprising:
an analog cell configured to provide an output signal having an analog value that is a continuous function of an analog value of an input signal to the analog cell, the analog cell including:
a p-type active zone extending in a first direction in an n-type well;
an n-type active zone extending in the first direction in a p-type well, wherein the p-type active zone is separated from the n-type active zone along a second direction that is different from the first direction;
a first transistor including a first gate electrode configured to control the output signal, the first gate electrode extending in the second direction over the p-type active zone;
an n-type pick-up region in the n-type well, wherein an n-type dopant concentration of the n-type pick-up region is higher than an n-type dopant concentration of the n-type well;
a p-type pick-up region in the p-type well, wherein a p-type dopant concentration of the p-type pick-up region is higher than a p-type dopant concentration of the p-type well;
a first gate-strip over the n-type pick-up region and aligned with the first gate electrode;
a first power rail extending in the first direction and spaced apart from the n-type pick-up region along the second direction;
a second power rail extending in the first direction and spaced apart from the p-type pick-up region along the second direction;
a first conductive segment extending in the second direction, wherein the n-type pick-up region is conductively connected to the first power rail with the first conductive segment;
a second conductive segment extending in the second direction, wherein the p-type pick-up region is conductively connected to the second power rail with the second conductive segment;
a first dummy gate extending in the second direction over the p-type active zone; and
a second dummy gate extending in the second direction over the n-type active zone.
20. The integrated circuit of claim 19 , further comprising:
a third dummy gate extending in the second direction over the n-type pick-up region; and
a fourth dummy gate extending in the second direction over the p-type pick-up region.