Power electronic device assemblies having an electrically insulating S-cell
View Patent ↗In one embodiment, a power electronics assembly includes a power device assembly further including an S-cell. The S-cell includes a first metal layer having a recess, a graphite layer bonded to the first metal layer, a second metal layer bonded to the graphite layer, and a ceramic layer, wherein the ceramic layer has a first metalized surface and a second metalized surface, and the first metalized surface is bonded to the second metal layer by a solder layer. The power electronics assembly further includes a power device disposed within the recess of the first metal layer, and a cold plate, wherein the second metalized surface of the ceramic layer is bonded to a surface of the cold plate.
1. A power electronics assembly comprising:
a power device assembly comprising:
an S-cell comprising:
a first metal layer comprising a recess;
a graphite layer bonded to the first metal layer;
a second metal layer bonded to the graphite layer; and
a ceramic layer, wherein the ceramic layer comprises a first metalized surface and a second metalized surface, and the first metalized surface is bonded to the second metal layer by a solder layer;
a power device disposed within the recess of the first metal layer; and
a cold plate, wherein the second metalized surface of the ceramic layer is bonded to a surface of the cold plate.
2. The power electronics assembly of claim 1 , wherein the first metalized surface and the second metalized surface comprises Ti—TiW—Cu—Ni—Au.
3. The power electronics assembly of claim 1 , wherein the second metalized surface of the ceramic layer is bonded to the surface of the cold plate by one of a solder and a metalized epoxy.
4. The power electronics assembly of claim 1 , wherein the power device assembly is embedded within one or more circuit board layers.
5. The power electronics assembly of claim 1 , further comprising a first active brazing layer between the first metal layer and the graphite layer and a second active brazing layer between the second metal layer and the ceramic layer.
6. The power electronics assembly of claim 1 , wherein the first metalized surface does not extend to a perimeter edge of a first surface of the ceramic layer and the second metalized surface does not extend to a perimeter edge of a second surface of the ceramic layer.
7. The power electronics assembly of claim 1 , further comprising a printed circuit board comprising:
a first dielectric layer comprising a power device opening, wherein the power device is disposed within the power device opening;
a second dielectric layer disposed on the first dielectric layer and the power device;
a first power layer comprising one or more first electrically conductive regions separated by one or more insulation regions;
a third dielectric layer disposed on the first power layer;
a second power layer disposed on the third dielectric layer comprising one or more second electrically conductive regions; and
a plurality of electroplated vias extending through one or more of the second dielectric layer, the first power layer, the third dielectric layer, and the second power layer.
8. A power electronics assembly comprising:
a power device assembly comprising:
an S-cell comprising:
a first metal layer comprising a recess;
a first graphite layer bonded to the first metal layer;
a ceramic layer comprising a first metalized surface and a second metalized surface, wherein the first metalized surface is bonded to the first graphite layer;
a second graphite layer bonded to the second metalized surface of the ceramic layer;
a second metal layer bonded to the second graphite layer; and
a power device disposed within the recess of the surface; and
a cold plate, wherein the second metal layer is bonded to a surface of the cold plate.
9. The power electronics assembly of claim 8 , wherein the first metalized surface and the second metalized surface comprises Ti—TiW—Cu—Ni—Au.
10. The power electronics assembly of claim 8 , wherein the second metal layer is bonded to the surface of the cold plate by one of a solder and a metalized epoxy.
11. The power electronics assembly of claim 8 , wherein the power device assembly is embedded within one or more circuit board layers.
12. The power electronics assembly of claim 8 , further comprising a first active brazing layer between the first metal layer and the first graphite layer, a second active brazing layer between the first graphite layer and the first metalized surface of the ceramic layer, a third active brazing layer between the second metalized surface of the ceramic layer and the second graphite layer, and a fourth active brazing layer between the second graphite layer and the second metal layer.
13. The power electronics assembly of claim 8 , wherein the first metalized surface does not extend to a perimeter edge of a first surface of the ceramic layer and the second metalized surface does not extend to a perimeter edge of a second surface of the ceramic layer.
14. The power electronics assembly of claim 8 , further comprising a printed circuit board comprising:
a first dielectric layer comprising a power device opening, wherein the power device is disposed within the power device opening;
a second dielectric layer disposed on the first dielectric layer and the power device;
a first power layer comprising one or more first electrically conductive regions separated by one or more insulation regions;
a third dielectric layer disposed on the first power layer;
a second power layer disposed on the third dielectric layer comprising one or more second electrically conductive regions; and
a plurality of electroplated vias extending through one or more of the second dielectric layer, the first power layer, the third dielectric layer, and the second power layer.
15. A method of fabricating a power electronics device assembly, the method comprising:
fabricating one or more power device assemblies by:
bonding a first metal layer to a first surface of a graphite layer;
bonding a second metal layer to a second surface of the graphite layer;
bonding the second metal layer to a first metalized surface of a ceramic layer;
forming a recess within the first metal layer; and
disposing a power device within the recess.
16. The method of claim 15 , further comprising inserting the one or more power device assemblies into one or more openings of a first dielectric layer.
17. The method of claim 16 , further comprising bonding the one or more power device assemblies and the first dielectric layer to a surface of a cold plate by a bonding layer.
18. The method of claim 17 , wherein the bonding layer is one of a solder layer and a metalized epoxy.
19. The method of claim 17 , further comprising:
disposing a second dielectric layer on the one or more power device assemblies and the first dielectric layer;
disposing a power layer subassembly on the second dielectric layer, the power layer subassembly comprising a first power layer comprising one or more first electrically conductive regions separated by one or more insulation regions, a third dielectric layer, and a second power layer disposed on the third dielectric layer;
drilling a plurality of first vias through the second power layer and the third dielectric layer, and laser drilling a plurality of second vias through the second power layer, the third dielectric layer, the first power layer, and the second dielectric layer;
electroplating the plurality of first vias and the plurality of second vias; and
etching the second power layer to form a plurality of second electrically conductive regions.
20. The method of claim 19 , wherein the second power layer is etched by a laser etching process.