Semiconductor device
A semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data holding circuit, a second data holding circuit, a third data holding circuit, a fourth data holding circuit, and an input line. A characteristic value of the memory cell is changeable by controlling the switch connected to the first data line among the plurality of switches based on a value held by the third data holding circuit and by controlling the switch connected to the second data line among the plurality of switches based on a value held by the fourth data holding circuit.
1. A semiconductor device comprising:
a first data line;
a second data line;
a memory cell connected to the first data line and the second data line; and
a determination circuit connected to the first data line and the second data line,
wherein the memory cell includes:
a plurality of switches connected to the first data line and the second data line;
a first data holding circuit;
a second data holding circuit;
a third data holding circuit;
a fourth data holding circuit;
an input line and
a current path selection circuit configured to adjust a current path within the memory cell based on values stored in the third data holding circuit and the fourth data holding circuit to reduce variations in characteristic values among multiple memory cells,
wherein the memory cell is configured to perform a product-sum operation by:
activating a switch among the plurality of switches that connects the memory cell to the first data line based on a value stored in the first data holding circuit and input data supplied to the input line; and
activating a switch among the plurality of switches that connects the memory cell to the second data line based on a value stored in the second data holding circuit and the input data supplied to the input line, and
wherein the current path selection circuit adjusts the activation of the switches based on values stored in the third data holding circuit and the fourth data holding circuit, thereby modifying current flow through the memory cell to align characteristic values across multiple memory cells within a memory array.
2. The semiconductor device according to claim 1 ,
wherein a plurality of memory cells, which are composed of the memory cell, are connected to the first data line and the second data line,
wherein input data is supplied in parallel to the input line of each of the plurality of memory cells,
wherein in the plurality of memory cells, a result of the product operation is outputted to the first data line and the second data line, the result being obtained from the input data and data stored in the first data holding circuit and the second data holding circuit, and
wherein a sum operation of data outputted from the plurality of memory cells is performed.
3. The semiconductor device according to claim 2 ,
wherein a reference cell is connected to the first data line and the second data line and supplies a reference value of the characteristic value,
wherein a current path is selected based on the values stored in the third data holding circuit and the fourth data holding circuit to align the characteristic value with respect to the reference value.
4. The semiconductor device according to claim 3 , further comprising a plurality of current sources commonly connected to the plurality of memory cells,
wherein any of the plurality of current sources are selectable based on a current value in adjusting the current path.
5. The semiconductor device according to claim 2 ,
wherein each of the first data holding circuit, the second data holding circuit, the third data holding circuit, and the fourth data holding circuit is composed of a SRAM,
wherein the SRAM is operable in a first operating state and in a second operating state that consumes less power than the first operating state, and
wherein a product-sum operation is performed in the second operating state.
6. The semiconductor device according to claim 1 ,
wherein each of the first data holding circuit and the second data holding circuit is configured by a SRAM formed in a first layout, and
wherein each of the third data holding circuit and the fourth data holding circuit is configured by a SRAM formed in a second layout.