Design structure for implementing matrix-based search capability in content addressable memory devices
View Patent ↗A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.
1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
a content addressable memory (CAM) device, including an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction; and
compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation, wherein the design structure comprises a netlist describing the CAM device.
2. The design structure of claim 1 , further comprising:
a write word line associated with each row of the array;
a pair of search lines associated with each cell of the array;
a row-oriented match line associated with each row of the array; and
a column-oriented match line associated with each column of the array;
wherein, for the matrix-based data comparison operation, search results for each individual cell are indicated on both the corresponding row-oriented match line and column-oriented match line associated therewith.
3. The design structure of claim 2 , wherein the array of memory cells comprises ternary CAM (TCAM) cells.
4. The design structure of claim 3 , wherein each of the TCAM cells further comprises:
a first SRAM storage device configured to store a first data bit and a second SRAM storage device configured to store a second data bit;
a first NFET stack associated with the first SRAM storage device and a first of the pair of search lines, and a second NFET stack associated with the second SRAM storage device and a second of the pair of search lines, the first and second NFET stacks comprising the compare circuitry configured to indicate match results on the associated row-oriented match line of the array; and
a third NFET stack associated with the first SRAM storage device and the first of the pair of search lines, and a fourth NFET stack associated with the second SRAM storage device and the second of the pair of search lines, the third and fourth NFET stacks comprising the compare circuitry configured to indicate match results on the associated column-oriented match line of the array.
5. The design structure of claim 4 , wherein the first and third NFET stacks are coupled to the same data node within the first SRAM storage device, and wherein the second and fourth NFET stacks are coupled to the same data node within the second SRAM storage device.
6. The design structure of claim 3 , wherein each of the TCAM cells further comprises:
a first SRAM storage device configured to store a first data bit and a second SRAM storage device configured to store a second data bit;
a first NFET device associated with a first data node of the first SRAM storage device and a first of the pair of search lines, a second NFET device associated with a second data node of the first SRAM storage device and a second of the pair of search lines, and a third NFET device coupled in series with the associated row-oriented match line of the array, the third NFET device having a gate terminal coupled between the first and second NFET devices, and wherein the first, second and third NFET devices comprise the compare circuitry configured to indicate match results on the associated row-oriented match line of the array;
a fourth NFET device associated with the first data node of the first SRAM storage device and the first of the pair of search lines, a fifth NFET device associated with the second data node of the first SRAM storage device and the second of the pair of search lines, and a sixth NFET device coupled in series with the associated column-oriented match line of the array, the sixth NFET device having a gate terminal coupled between the fourth and fifth NFET devices, and wherein the fourth, fifth and sixth NFET devices comprise the compare circuitry configured to indicate match results on the associated column-oriented match line of the array; and
a first parallel pass gate in parallel with the third NFET device, the first parallel pass gate associated with a data node of the second SRAM storage device, and a second parallel pass gate in parallel with the sixth NFET device, the second parallel pass gate also associated with the data node of the second SRAM storage device.
7. The design structure of claim 6 , wherein the first and fourth NFET devices are coupled to the same data node within the first SRAM storage device, and wherein the second and fifth NFET devices are both coupled to the opposite data node within the first SRAM storage device, with respect to the first and fourth NFET devices.
8. The design structure of claim 2 , wherein each of the CAM cells further comprises:
an SRAM storage device configured to store a data bit;
a first NFET stack associated with the SRAM storage device and a first of the pair of search lines, and a second NFET stack associated the SRAM storage device and a second of the pair of search lines, the first and second NFET stacks comprising the compare circuitry configured to indicate match results on the associated row-oriented match line of the array; and
a third NFET stack associated with the SRAM storage device and first of the pair of search lines, and a fourth NFET stack associated with the SRAM storage device and the second of the pair of search lines, the third and fourth NFET stacks comprising the compare circuitry configured to indicate match results on the associated column-oriented match line of the array.
9. The design structure of claim 8 , wherein the first and third NFET stacks are coupled to one data node within the SRAM storage device, and wherein the second and fourth NFET stacks are coupled to a complementary data node within the SRAM storage device.
10. The design structure of claim 2 , wherein each of the CAM cells further comprises:
an SRAM storage device configured to store a data bit;
a first NFET device associated with the SRAM storage device and a first of the pair of search lines, a second NFET device associated with the SRAM storage device and a second of the pair of search lines, and a third NFET device coupled in series with the associated row-oriented match line of the array, the third NFET device having a gate terminal coupled between the first and second NFET devices, and wherein the first, second and third NFET devices comprise the compare circuitry configured to indicate match results on the associated row-oriented match line of the array; and
a fourth NFET device associated with the SRAM storage device and the first of the pair of search lines, a fifth NFET device associated with the SRAM storage device and the second of the pair of search lines, and a sixth NFET device coupled in series with the associated column-oriented match line of the array, the sixth NFET device having a gate terminal coupled between the fourth and fifth NFET devices, and wherein the fourth, fifth and sixth NFET devices comprise the compare circuitry configured to indicate match results on the associated column-oriented match line of the array.
11. The design structure of claim 10 , wherein the first and fourth NFET devices are coupled to one data node within the SRAM storage device, and wherein the second and fifth NFET devices are coupled to a complementary data node within the SRAM storage device.
12. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
13. The design structure of claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, programming data, or design specifications.