Memory device
View Patent ↗A memory device includes a first static random access memory (SRAM) cell, a second SRAM cell, and a first metal layer. The first SRAM cell includes a first write-port pull-up (PU) transistor and a second write-port PU transistor arranged in a Y-direction, and a first read-port PD transistor and a first read-port PG transistor. The second SRAM cell includes a third write-port PU transistor and a fourth write-port PU transistor arranged in the Y-direction, and a second read-port PD transistor and a second read-port PG transistor. The first and second read-port PD transistors and the first and second read-port PG transistors are arranged in the Y-direction. The first metal layer is over the first SRAM cell and the second SRAM cell. The first metal layer includes a read bit-line conductor extending in the Y-direction and shared by the first SRAM cell and the second SRAM cell.
1. A memory device, comprising:
a first static random access memory (SRAM) cell comprising:
a first write-port pull-up (PU) transistor and a second write-port PU transistor arranged in a Y-direction; and
a first read-port pull-down (PD) transistor and a first read-port pass-gate (PG) transistor;
a second SRAM cell comprising:
a third write-port PU transistor and a fourth write-port PU transistor arranged in the Y-direction; and
a second read-port PD transistor and a second read-port PG transistor; and
a first metal layer over the first SRAM cell and the second SRAM cell, wherein the first metal layer comprises a read bit-line conductor extending in the Y-direction and shared by the first SRAM cell and the second SRAM cell,
wherein the first read-port PD transistor, the first read-port PG transistor, the second read-port PD transistor, and the second read-port PG transistor are arranged in the Y-direction.
2. The memory device of claim 1 , wherein the first SRAM cell further comprises a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, and a second write-port PG transistor sharing a second active area extending in the Y-direction,
wherein the second SRAM cell further comprises a third write-port PD transistor, a fourth write-port PD transistor, a third write-port PG transistor, and a fourth write-port PG transistor sharing a fifth active area extending in the Y-direction,
wherein the first write-port PU transistor, the first write-port PD transistor, and the first read-port PD transistor share a first gate structure extending in an X-direction perpendicular to the Y-direction,
wherein the third write-port PU transistor, the third write-port PD transistor, and the second read-port PD transistor share a second gate structure extending in the X-direction.
3. The memory device of claim 2 , wherein the read bit-line conductor is electrically connected to a source/drain feature of the first read-port PG transistor and a source/drain feature of the second read-port PG transistor.
4. The memory device of claim 3 , wherein the first metal layer further comprises a first metal conductor and a second metal conductor extending in the Y-direction and electrically coupled to a reference voltage, wherein the memory device further comprises:
a source/drain contact extending in the X-direction, wherein the source/drain contact is electrically connected to a source/drain feature shared by the first read-port PD transistor and second read-port PD transistor, a source/drain feature shared by the first write-port PD transistor and the second write-port PD transistor, and a source/drain feature shared by the third write-port PD transistor and the fourth write-port PD transistor, wherein the first metal conductor and the second metal conductor are electrically connected to the source/drain contact.
5. The memory device of claim 2 , further comprising:
a second metal layer over the first metal layer, wherein the second metal layer comprises a first write word-line conductor and a second write word-line conductor extending in the X-direction,
wherein the first write word-line conductor is electrically connected to gate structures of the first write-port PG transistor and the second write-port PG transistor,
wherein the second write word-line conductor is electrically connected to gate structures of the third write-port PG transistor and the fourth write-port PG transistor.
6. The memory device of claim 5 , further comprising:
a third metal layer over the second metal layer, wherein the third metal layer comprises a first write bit-line conductor and a second write bit-line conductor extending in the Y-direction,
wherein the first write bit-line conductor is electrically connected to a source/drain feature of the first write-port PG transistor,
wherein the second write bit-line conductor is electrically connected to a source/drain feature of the third write-port PG transistor.
7. The memory device of claim 6 , wherein the third metal layer further comprises a first write bit-line-bar conductor and a second write bit-line-bar conductor extending in the Y-direction,
wherein the first write bit-line-bar conductor is electrically connected to a source/drain feature of the second write-port PG transistor,
wherein the second write bit-line-bar conductor is electrically connected to a source/drain feature of the fourth write-port PG transistor.
8. The memory device of claim 7 , further comprising:
a fourth metal layer over the third metal layer, wherein the third metal layer comprises a first read word-line conductor and a second read word-line conductor extending in the X-direction,
wherein the first read word-line conductor is electrically connected to a gate structure of the first read-port PG transistor,
wherein the second read word-line conductor is electrically connected to a gate structure of the second read-port PG transistor.
9. The memory device of claim 2 , wherein the read bit-line conductor is electrically connected to a source/drain feature shared by the first read-port PD transistor and the second read-port PD transistor.
10. The memory device of claim 9 , wherein the first metal layer further comprises a first metal conductor and a second metal conductor electrically coupled to a reference voltage,
wherein the first metal conductor electrically connects a source/drain contact over a source/drain feature shared by the first write-port PD transistor and the second write-port PD transistor to a source/drain contact over a source/drain feature of the second read-port PG transistor,
wherein the second metal conductor electrically connects a source/drain contact over a source/drain feature shared by the third write-port PD transistor and the fourth write-port PD transistor to a source/drain contact over a source/drain feature of the first read-port PG transistor.
11. A memory device, comprising:
a first static random access memory (SRAM) cell comprising:
a first write-port pull-up (PU) transistor and a second write-port PU transistor sharing a first active area extending in a Y-direction;
a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, and a second write-port PG transistor sharing a second active area extending in the Y-direction; and
a first read-port PD transistor and a first read-port PG transistor sharing a third active area extending in the Y-direction;
a second SRAM cell comprising:
a third write-port PU transistor and a fourth write-port PU transistor sharing a fourth active area extending in the Y-direction;
a third write-port PD transistor, a fourth write-port PD transistor, a third write-port PG transistor, and a fourth write-port PG transistor sharing a fifth active area extending in the Y-direction; and
a second read-port PD transistor and a second read-port PG transistor sharing the third active area; and
a first metal layer over the first SRAM cell and the second SRAM cell, wherein the first metal layer comprises a read bit-line conductor extending in the Y-direction and shared by the first SRAM cell and the second SRAM cell.
12. The memory device of claim 11 , wherein the first SRAM cell and the second SRAM cell respectively have a first non-rectangular cell boundary and a second non-rectangular cell boundary.
13. The memory device of claim 12 , wherein the first metal layer further comprises a first write word-line landing pad and a second write word-line landing pad extending in the Y-direction,
wherein the first write word-line landing pad lengthwise overlaps the first non-rectangular cell boundary in a top view and is electrically connected to gate structures of the first write-port PG transistor and the second write-port PG transistor,
wherein the second write word-line landing pad lengthwise overlaps the second non-rectangular cell boundary in the top view and is electrically connected to gate structures of the third write-port PG transistor and the fourth write-port PG transistor,
wherein the memory device further comprises a second metal layer over the first metal layer, wherein the second metal layer comprises a first write word-line conductor electrically connected to the first write word-line landing pad and a second write word-line conductor electrically connected to the second write word-line landing pad.
14. The memory device of claim 11 , wherein the first metal layer further comprises a first metal conductor and a second metal conductor extending in the Y-direction and electrically coupled to a voltage source,
wherein the first metal conductor overlaps the first active area in a top view and is electrically connected to a source/drain feature shared by the first write-port PU transistor and the second write-port PU transistor,
wherein the second metal conductor overlaps the fourth active area in the top view and is electrically connected to a source/drain feature shared by the third write-port PU transistor and the fourth write-port PU transistor.
15. The memory device of claim 12 , further comprising:
a first source/drain contact extending in an X-direction and over a source/drain feature shared by the first write-port PD transistor and the second write-port PD transistor, wherein the X-direction is perpendicular to the Y-direction;
a second source/drain contact extending in the X-direction and over a source/drain feature shared by the third write-port PD transistor and the fourth write-port PD transistor;
a third source/drain contact lengthwise overlapping the first non-rectangular cell boundary in a top view and over a source/drain feature of the first read-port PG transistor;
a fourth source/drain contact lengthwise overlapping the second non-rectangular cell boundary in the top view and over a source/drain feature of the second read-port PG transistor;
a first metal conductor in the first metal layer and electrically connected to the first source/drain contact and the fourth source/drain contact; and
a second metal conductor in the first metal layer and electrically connected to the second source/drain contact and the third source/drain contact.
16. The memory device of claim 15 , wherein the first metal conductor and the second metal conductor each has an L-shape in the top view.
17. A memory device, comprising:
a first static random access memory (SRAM) cell comprising:
a first write-port pull-up (PU) transistor and a second write-port PU transistor sharing a first active area extending in a Y-direction;
a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, and a second write-port PG transistor sharing a second active area extending in the Y-direction; and
a first read-port PD transistor and a first read-port PG transistor sharing a third active area extending in the Y-direction;
a second SRAM cell comprising:
a third write-port PU transistor and a fourth write-port PU transistor sharing a fourth active area extending in the Y-direction;
a third write-port PD transistor, a fourth write-port PD transistor, a third write-port PG transistor, and a fourth write-port PG transistor sharing a fifth active area extending in the Y-direction; and
a second read-port PD transistor and a second read-port PG transistor sharing the third active area;
a first metal layer over the first SRAM cell and the second SRAM cell, wherein the first metal layer comprises a read bit-line conductor extending in the Y-direction and shared by the first SRAM cell and the second SRAM cell; and
a second metal layer over the first metal layer, wherein the second metal layer comprises a first write word-line conductor for the first SRAM cell and a second write word-line conductor for the second SRAM cell extending in an X-direction perpendicular to the Y-direction.
18. The memory device of claim 17 , wherein the first SRAM cell and the second SRAM cell respectively have a first L-shaped cell boundary and a second L-shaped cell boundary in a top view.
19. The memory device of claim 18 , further comprising:
a source/drain contact extending in the X-direction, over a source/drain feature shared by the first read-port PD transistor and the second read-port PD transistor, and lengthwise overlapping the first L-shaped cell boundary and the second L-shaped cell boundary,
wherein the read bit-line conductor is electrically connected to the source/drain contact.
20. The memory device of claim 18 , further comprising:
a first source/drain contact extending in the X-direction, over a source/drain feature of the first read-port PG transistor, and lengthwise overlapping the first L-shaped cell boundary; and
a second source/drain contact extending in the X-direction, over a source/drain feature of the second read-port PG transistor, and lengthwise overlapping the second L-shaped cell boundary,
wherein the read bit-line conductor is electrically connected to the first source/drain contact and the second source/drain contact.