Integrated circuit devices including stacked field effect transistors and methods of forming the same
Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and a first gate structure on the first channel region. A lower surface of the first source/drain region may be higher than a lower surface of the first gate structure relative to the substrate.
1. An integrated circuit device comprising:
a substrate; and
a transistor stack on the substrate, the transistor stack comprising a first transistor and a second transistor on the first transistor,
wherein the first transistor is between the substrate and the second transistor and wherein the first transistor comprises:
first and second source/drain regions;
a first channel region between the first and second source/drain regions; and
a first gate structure on the first channel region,
wherein a lower surface of the first source/drain region is higher than a lower surface of the first gate structure relative to the substrate, and
wherein the lower surface of the first source/drain region is higher than a lower surface of the second source/drain region relative to the substrate.
2. The integrated circuit device of claim 1 , further comprising a bottom insulating layer between the lower surface of the first source/drain region and the substrate.
3. The integrated circuit device of claim 2 , wherein an upper surface of the bottom insulating layer contacts the lower surface of the first source/drain region.
4. The integrated circuit device of claim 2 , wherein the lower surface of the first gate structure is coplanar with a lower surface of the bottom insulating layer.
5. The integrated circuit device of claim 1 , further comprising a top contact contacting an upper surface of the first source/drain region.
6. The integrated circuit device of claim 1 , wherein the substrate and the second transistor are spaced apart from each other in a direction,
the first channel region comprises a plurality of first channel regions stacked in the direction, and
the lower surface of the first source/drain region is coplanar with a lower surface of a lowermost first channel region of the plurality of first channel regions.
7. The integrated circuit device of claim 1 , wherein the substrate and the second transistor are spaced apart from each other in a direction,
the first channel region comprises a plurality of first channel regions stacked in the direction, and
a lower portion of the first gate structure is between the substrate and a lowermost first channel region of the plurality of first channel regions.
8. The integrated circuit device of claim 1 , wherein the lower surface of the second source/drain region is higher than the lower surface of the first gate structure relative to the substrate.
9. The integrated circuit device of claim 8 , further comprising:
a first bottom insulating layer between the lower surface of the first source/drain region and the substrate; and
a second bottom insulating layer between the lower surface of the second source/drain region and the substrate.
10. The integrated circuit device of claim 8 , further comprising:
a first top contact contacting an upper surface of the first source/drain region; and
a second top contact contacting an upper surface of the second source/drain region.
11. The integrated circuit device of claim 1 , further comprising a bottom contact in the substrate and electrically connected to the second source/drain region.
12. An integrated circuit device comprising:
a substrate; and
a transistor stack on the substrate, the transistor stack comprising a first transistor and a second transistor on the first transistor,
wherein the first transistor is between the substrate and the second transistor and comprises:
first and second source/drain regions;
a first channel region between the first and second source/drain regions; and
a first gate structure on the first channel region and between the first and second source/drain regions,
wherein an uppermost end of the second source/drain region is spaced apart from the substrate by a first distance, and an upper surface of the first gate structure is spaced apart from the substrate by a second distance that is greater than the first distance.
13. The integrated circuit device of claim 12 , wherein an uppermost end of the first source/drain region is spaced apart from the substrate by a third distance that is greater than the first distance.
14. The integrated circuit device of claim 12 , wherein the substrate and the second transistor are spaced apart from each other in a direction,
the first channel region comprises a plurality of first channel regions stacked in the direction, and
a lowermost end of the upper surface of the second source/drain region is spaced apart from the substrate by a fourth distance, and an upper surface of an uppermost first channel region of the plurality of first channel regions is spaced apart from the substrate by a fifth distance that is equal to the fourth distance.
15. The integrated circuit device of claim 12 , further comprising a bottom contact in the substrate and electrically connected to the second source/drain region.
16. A method of forming an integrated circuit device, the method comprising:
forming a preliminary transistor stack on a substrate, the preliminary transistor stack comprising an upper channel region and a lower channel region that is between the substrate and the upper channel region;
forming a bottom insulating layer on the substrate and adjacent a first side surface of the lower channel region;
forming a first source/drain region on the bottom insulating layer, the first source/drain region contacting the first side surface of the lower channel region; and
forming a second source/drain region that is on the substrate and contacts a second side surface of the lower channel region,
wherein an uppermost end of the second source/drain region is lower than an uppermost end of the first source/drain region relative to the substrate.
17. The method of claim 16 , further comprising:
forming an insulating layer on the first source/drain region; and
forming a top contact in the insulating layer, wherein the top contact is electrically connected to the first source/drain region.
18. The method of claim 16 ,
wherein the first side surface of the lower channel region is opposite the second side surface of the lower channel region.
19. The method of claim 18 , wherein forming the second source/drain region comprises:
forming a preliminary second source/drain region that is on the substrate and contacts the second side surface the of the lower channel region; and
forming the second source/drain region by removing an upper portion of the preliminary second source/drain region.