Nanosheet semiconductor device and method for manufacturing the same
A method for manufacturing a nanosheet semiconductor device includes: forming a liner layer to cover first and second fin structures, each of the fin structures including a stacked structure, a poly gate disposed on the stacked structure, and inner spacers, the stacked structure including sacrificial features covered by the inner spacers, and channel features disposed to alternate with the sacrificial features; forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that interconnects the upper and lower portions and that laterally covers the liner layer; subjecting the upper and lower portions to a directional treatment; and removing the upper and interconnecting portions of the dielectric layer and a portion of the liner layer, to form a liner and a bottom dielectric insulator disposed on the liner.
1 . A method for manufacturing a nanosheet semiconductor device, comprising:
forming a liner layer to cover a first fin structure and a second fin structure that are disposed on a substrate and that are spaced apart from each other in a first direction, each of the first fin structure and the second fin structure including a stacked structure disposed on the substrate, a poly gate disposed on the stacked structure in a second direction transverse to the first direction, and a plurality of inner spacers, the stacked structure including a plurality of sacrificial features and a plurality of channel features disposed to alternate with the plurality of sacrificial features in the second direction, the plurality of inner spacers laterally covering the plurality of sacrificial features;
forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that extends in the second direction to interconnect the upper portion and the lower portion and that laterally covers the liner layer;
subjecting the upper portion and the lower portion of the dielectric layer to a directional treatment, so that the upper portion and the lower portion of the dielectric layer are denser than the interconnecting portion of the dielectric layer; and
removing the upper portion and the interconnecting portion of the dielectric layer and a portion of the liner layer, so as to form a liner on the substrate and a bottom dielectric insulator that is disposed on the liner and that is separated from the substrate by the liner.
2 . The method of claim 1 , wherein the liner layer is formed by thermal chemical vapor deposition.
3 . The method of claim 2 , wherein the thermal chemical vapor deposition is conducted at a temperature ranging from 450° C. to 550° C.
4 . The method of claim 2 , wherein the thermal chemical vapor deposition is conducted for a deposition period ranging from 60 seconds to 120 seconds.
5 . The method of claim 2 , wherein a gas used in the thermal chemical vapor deposition includes chlorosilane, ammonia, oxygen gas, methane, ethane, ethylene, propylene, hydrocarbon, tetramethyldisiloxane, silicon-containing hydrocarbon, or combinations thereof.
6 . The method of claim 1 , wherein the liner layer has a thickness ranging from 1 nm to 5 nm.
7 . The method of claim 1 , wherein the liner layer includes silicon nitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof.
8 . A method for manufacturing a nanosheet semiconductor device, comprising:
forming a liner layer to cover a first fin structure and a second fin structure that are disposed on a substrate and that are spaced apart from each other by a trench in a first direction, each of the first fin structure and the second fin structure including a stacked structure disposed on the substrate, a poly gate disposed on the stacked structure in a second direction transverse to the first direction, and a plurality of inner spacers, the stacked structure including a plurality of sacrificial features and a plurality of channel features disposed to alternate with the plurality of sacrificial features in the second direction, the plurality of inner spacers laterally covering the plurality of sacrificial features;
forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that extends in the second direction to interconnect the upper portion and the lower portion and that laterally covers the liner layer;
subjecting the upper portion and the lower portion of the dielectric layer to a directional treatment, so that the upper portion and the lower portions of the dielectric layer are denser than the interconnecting portion of the dielectric layer;
forming an anti-reflection layer in the trench such that the upper portion and a part of the interconnecting portion of the dielectric layer are exposed from the anti-reflection layer;
etching away the upper portion and the part of the interconnecting portion of the dielectric layer; and
removing the anti-reflection layers, a remaining part of the interconnecting portion of the dielectric layer, and a portion of the liner layer, so as to form a liner on the substrate and a bottom dielectric insulator that is disposed on the liner and that is separated from the substrate by the liner.
9 . The method of claim 8 , wherein the liner layer is formed by thermal chemical vapor deposition.
10 . The method of claim 9 , wherein the thermal chemical vapor deposition is conducted at a temperature ranging from 450° C. to 550° C.
11 . The method of claim 9 , wherein the thermal chemical vapor deposition is conducted for a deposition period ranging from 60 seconds to 120 seconds.
12 . The method of claim 9 , wherein a gas used in the thermal chemical vapor deposition includes chlorosilane, ammonia, oxygen gas, methane, ethane, ethylene, propylene, hydrocarbon, tetramethyldisiloxane, silicon-containing hydrocarbon, or combinations thereof.
13 . The method of claim 9 , wherein the liner layer has a thickness ranging from 1 nm to 5 nm.
14 . The method of claim 9 , wherein the liner layer includes silicon nitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or combinations thereof.
15 . A method for manufacturing a nanosheet semiconductor device, comprising:
forming a liner layer to cover a first fin structure and a second fin structure that are disposed on a substrate and that are spaced apart from each other in a first direction, each of the first fin structure and the second fin structure including a stacked structure disposed on the substrate, a poly gate disposed on the stacked structure in a second direction transverse to the first direction, and a plurality of inner spacers, the stacked structure including a plurality of sacrificial features and a plurality of channel features disposed to alternate with the plurality of sacrificial features in the second direction, the plurality of inner spacers laterally covering the plurality of sacrificial features;
forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that extends in the second direction to interconnect the upper portion and the lower portion and that laterally covers the liner layer;
subjecting the upper portion and the lower portion of the dielectric layer to a directional treatment, so that the upper portion and the lower portion of the dielectric layer are denser than the interconnecting portion of the dielectric layer;
removing the upper portion and the interconnecting portion of the dielectric layer and a portion of the liner layer, so as to form a liner on the substrate and a bottom dielectric insulator that is disposed on the liner and that is separated from the substrate by the liner; and
forming a source/drain region on the liner and the bottom dielectric insulator.
16 . The method of claim 15 , wherein a vertical distance between a topmost point of the liner and a top surface of the substrate ranges from 1 nm to 10 nm.
17 . The method of claim 15 , wherein a vertical distance between a bottommost point of a lower surface of the liner and a top surface of the substrate ranges from 3 nm to 20 nm.
18 . The method of claim 15 , wherein a topmost point of the liner is located at a level between an upper surface of a lowermost one of the plurality of inner spacers and a lower surface of the lowermost one of the plurality of inner spacers, the lowermost one of the plurality of inner spacers being proximate to the substrate.
19 . The method of claim 15 , wherein the liner is formed to be in partial contact with a lowermost one of the plurality of inner spacers which is proximate to the substrate.
20 . The method of claim 15 , wherein an upper surface of the bottom dielectric insulator is formed to have a concave shape, and a distance between a bottommost point of the upper surface of the bottom dielectric insulator and a topmost point of the liner is greater than 0 nm and up to 15 nm.