Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization
A method for fabricating a semiconductor device includes forming a first inner spacer layer along a substrate and a nanosheet stack disposed on the substrate, performing an ultraviolet (UV) condensation process to form a hardened inner spacer from the first inner spacer layer, forming a second inner spacer layer along the hardened inner spacer, and removing material to form inner spacers by performing an inner spacer etch.
1. A method for fabricating a semiconductor device, comprising:
forming a first inner spacer layer along a substrate and a nanosheet stack disposed on the substrate, the nanosheet stack having alternating first and second layers including first and second semiconductor material, respectively;
performing an ultraviolet (UV) condensation process to form a hardened inner spacer from the first inner spacer layer;
forming a second inner spacer layer along the hardened inner spacer; and
forming inner spacers by performing an inner spacer etch.
2. The method of claim 1 , wherein the first semiconductor material includes silicon germanium (SiGe) and the second semiconductor material including silicon (Si).
3. The method of claim 1 , further comprising forming the nanosheet stack on the substrate.
4. The method of claim 3 , further comprising forming a sacrificial dummy gate structure on the nanosheet stack, the sacrificial dummy gate structure including sacrificial gate material and a mask disposed on the sacrificial gate material.
5. The method of claim 4 , further comprising forming a spacer along the sacrificial gate structure and the nanosheet stack.
6. The method of claim 1 , further comprising forming indentations within the nanosheet stack.
7. The method of claim 6 , wherein the indentations are formed within the first layers of the nanosheet stack.
8. The method of claim 1 , further comprising performing a second UV condensation process to form a second hardened inner spacer from the second inner spacer.
9. The method of claim 1 , further comprising:
forming source/drain regions on the substrate;
forming dielectric layers on the source/drain regions;
removing the sacrificial gate structure; and
removing the first layers from the nanosheet stack.
10. The method of claim 9 , wherein removing the sacrificial gate structure includes using a dummy gate pull process.
11. The method of claim 9 , wherein removing the first layers from the nanosheet stack includes using a channel release process.
12. A method for fabricating a semiconductor device, comprising:
forming a nanosheet stack on a silicon (Si) substrate, the nanosheet stack having alternating first and second layers including silicon germanium (SiGe) and Si, respectively;
forming a sacrificial dummy gate structure on the nanosheet stack;
forming a spacer along the sacrificial gate structure and the nanosheet stack;
forming indentations within the nanosheet stack;
forming a first inner spacer layer along the substrate and the nanosheet stack;
performing an ultraviolet (UV) condensation process to form a hardened inner spacer from the first inner spacer layer;
forming a second inner spacer layer along the hardened inner spacer; and
forming inner spacers by performing an inner spacer etch.
13. The method of claim 12 , wherein the indentations are formed within the first layers of the nanosheet stack.
14. The method of claim 12 , further comprising performing a second UV condensation process to form a second hardened inner spacer from the second inner spacer.
15. The method of claim 12 , further comprising:
forming source/drain regions on the substrate;
forming dielectric layers on the source/drain regions;
removing the sacrificial gate structure; and
removing the first layers from the nanosheet stack.
16. The method of claim 15 , wherein removing the sacrificial gate structure includes using a dummy gate pull process.
17. The method of claim 15 , wherein removing the first layers from the nanosheet stack includes using a channel release process.
18. A method for fabricating a semiconductor device, comprising:
performing an ultraviolet (UV) condensation process to form a hardened inner spacer from a first inner spacer layer, the first inner spacer layer being formed at least on a nanosheet stack disposed on a substrate;
forming a second inner spacer layer along the hardened inner spacer; and
forming inner spacers by performing an inner spacer etch.
19. The method of claim 18 , further comprising:
forming indentations within the nanosheet stack; and
after forming the indentations, forming the first inner spacer layer along the substrate and the nanosheet stack.
20. The method of claim 18 , further comprising performing a second UV condensation process to form a second hardened inner spacer from the second inner spacer.