Semiconductor device with active layers doped by sacrificial layers and method thereof
A semiconductor device includes a substrate including an active pattern, a channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, on the active pattern, a source/drain pattern connected to the plurality of semiconductor patterns, and a gate electrode including a first inner electrode provided below a first semiconductor pattern among the plurality of semiconductor patterns, on the plurality of semiconductor patterns, and a second inner electrode provided above the first semiconductor pattern, the first semiconductor pattern includes a first portion adjacent to the first inner electrode, a second portion adjacent to the second inner electrode, and a third portion between the first and second portions, the first semiconductor pattern includes a dopant having an atomic weight greater than that of silicon, and a dopant concentration of the third portion is smaller than a dopant concentration of each of the first and second portions.
1 . A semiconductor device comprising:
a substrate including an active region and a dummy region;
an active pattern on the active region and a dummy pattern on the dummy region;
a channel pattern and a source/drain pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked;
a dummy stacked pattern on the dummy pattern, the dummy stacked pattern horizontally spaced apart from the channel pattern and the source/drain pattern, and the dummy stacked pattern including a plurality of dummy sacrificial layers and a plurality of dummy layers, wherein the plurality of dummy sacrificial layers and the plurality of dummy layers are alternately stacked; and
a gate electrode on the plurality of semiconductor patterns, the gate electrode including an inner electrode interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns,
wherein each of the plurality of dummy sacrificial layers includes a dopant having an atomic weight greater than an atomic weight of each of silicon-germanium (SiGe) and silicon (Si), and
wherein a concentration of the dopant in the plurality of dummy sacrificial layers is in a range from greater than 1.0×10 20 atoms/cm 3 to 1.0×10 21 atoms/cm 3 ,
wherein the plurality of dummy layers include the dopant diffused from the plurality of dummy sacrificial layers, and
wherein a concentration of the diffused dopant is 1.0×10 17 atoms/cm 3 to 1.0×10 18 atoms/cm 3 .
2 . The semiconductor device of claim 1 , wherein the dopant includes at least one of phosphorous (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur(S), selenium (Se), tellurium (Te), gallium (Ga) and indium (In).
3 . The semiconductor device of claim 1 , wherein a concentration of germanium (Ge) in each of the plurality of dummy sacrificial layers is 5 at % to 40 at %.
4 . The semiconductor device of claim 1 , wherein each of the plurality of dummy layers includes undoped silicon (undoped Si).
5 . The semiconductor device of claim 1 , wherein
the dummy stacked pattern includes the plurality of dummy sacrificial layers stacked vertically and overlapping with the plurality of dummy layers, and
the dummy stacked pattern includes a silicon-germanium-dopant layer interposed between silicon-germanium (SiGe) layers.
6 . The semiconductor device of claim 5 , wherein the silicon-germanium-dopant layer does not include silicon-germanium-carbon (SiGeC).
7 . The semiconductor device of claim 1 , wherein the dummy stacked pattern includes the plurality of dummy sacrificial layers stacked vertically and overlapping with the plurality of dummy layers, and
wherein the dummy stacked pattern includes a silicon-germanium-dopant layer and a silicon-germanium layer which are alternately stacked.
8 . The semiconductor device of claim 7 , wherein the silicon-germanium-dopant layer does not include silicon-germanium-carbon (SiGeC).
9 . The semiconductor device of claim 1 , wherein
the gate electrode further includes a portion interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns, and
the semiconductor device further comprises
a gate insulating layer between the adjacent semiconductor patterns and the portion of the gate electrode,
an inner spacer between the gate insulating layer and the source/drain pattern;
a gate spacer on a sidewall of the gate electrode,
a gate capping pattern on a top surface of the gate electrode,
a sacrificial pattern on an uppermost dummy layer among the plurality of dummy layers,
a mask pattern on the sacrificial pattern,
an interlayer insulating layer on the gate capping pattern and the mask pattern,
an active contact electrically connected to the source/drain pattern through the interlayer insulating layer,
a metal-semiconductor compound layer interposed between the active contact and the source/drain pattern,
a gate contact passing through the interlayer insulating layer and the gate capping pattern to be electrically connected to the gate electrode,
a first metal layer on the interlayer insulating layer, the first metal layer including a power wiring and first wirings electrically connected to the active contact and the gate contact, respectively, and
a second metal layer on the first metal layer, the second metal layer including second wirings electrically connected to the first metal layer.
10 . A semiconductor device comprising:
a substrate including an active pattern;
a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked;
a source/drain pattern connected to the plurality of semiconductor patterns; and
a gate electrode on the plurality of semiconductor patterns, the gate electrode including a first inner electrode provided below a first semiconductor pattern among the plurality of semiconductor patterns, and a second inner electrode provided above the first semiconductor pattern,
wherein the first semiconductor pattern includes a first portion adjacent to the first inner electrode, a second portion adjacent to the second inner electrode, and a third portion between the first portion and the second portion,
wherein the first semiconductor pattern includes a dopant having an atomic weight greater than an atomic weight of silicon (Si),
wherein a dopant concentration of the third portion is smaller than a dopant concentration of each of the first and second portions,
wherein the dopant is diffused into each of the first and second portions of the first semiconductor pattern, and
wherein a concentration of the diffused dopant of each of the first and second portions is 1.0×10 17 atoms/cm 3 to 1.0×10 18 atoms/cm 3 .
11 . The semiconductor device of claim 10 , wherein the dopant includes at least one of phosphorous (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur(S), selenium (Se), tellurium (Te), gallium (Ga) and indium (In).
12 . The semiconductor device of claim 10 , wherein the third portion includes undoped silicon (undoped Si).
13 . The semiconductor device of claim 10 , wherein a dopant concentration of an uppermost second semiconductor pattern among the plurality of semiconductor patterns decreases toward an upper portion of the uppermost second semiconductor pattern.
14 . The semiconductor device of claim 10 , wherein the semiconductor patterns include the first semiconductor pattern with a first width in a first direction and a second semiconductor pattern with a second width in the first direction, the second semiconductor pattern being lower than the first semiconductor pattern, the second width being greater than the first width.