Semiconductor device having a varying thickness nanowire channel and method for fabricating the same
A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.
1. A transistor, comprising:
a drain;
a source;
a gate electrode;
a first nanowire between the source and drain; and
a gate spacer formed on opposite sidewalls of the gate electrode, wherein
the gate spacer includes a hole therein,
the first nanowire extends through the hole in the gate spacer to contact the source and drain,
the first nanowire has a first section with a first thickness and a second section with a second thickness different from the first thickness, wherein the second section is between the first section and at least one of the source or drain, the first nanowire to include a channel when a voltage is applied to the gate electrode,
the gate electrode surrounds a periphery of the first section, and
the gate spacer surrounds a periphery of the second section.
2. The transistor as claimed in claim 1 , wherein:
the first section overlaps the gate electrode, and
the second section does not overlap the gate electrode.
3. The transistor as claimed in claim 1 , wherein:
the first section does not overlap the gate spacer, and
the second section overlaps the gate spacer.
4. The transistor as claimed in claim 3 , wherein:
the gate spacer includes an outer spacer and an inner spacer on opposite sides of the hole,
the outer spacer is in contact with a side surface of the first nanowire, and
the inner spacer is in contact with a lower surface of the first nanowire.
5. The transistor as claimed in claim 1 , wherein:
the first section has a first surface,
the second section has a second surface, and
the first and second surfaces are in different planes.
6. The transistor as claimed in claim 1 , wherein the first and second sections of the first nanowire are arranged to have substantially a barbell shape.
7. The transistor as claimed in claim 1 , wherein the first nanowire has a third section between the first and second sections, and wherein the third section is inclined relative to the first and second sections.
8. The transistor as claimed in claim 1 , wherein:
the first nanowire includes at least one dimple, and
the at least one dimple is between a surface of the first section and a surface of the second section.
9. The transistor as claimed in claim 1 , wherein the second section has rounded surfaces.
10. The transistor as claimed in claim 1 , further comprising
a fin-shaped pattern overlapping at least one of the source, the drain, or the first nanowire.
11. The transistor as claimed in claim 1 , further comprising:
a second nanowire between the source and drain and overlapping the first nanowire.
12. The transistor as claimed in claim 11 , wherein the second nanowire has a different shape from the first nanowire.
13. The transistor as claimed in claim 11 , wherein the first and second nanowires have different cross-sectional areas.
14. The transistor as claimed in claim 1 , wherein the second thickness is greater than the first thickness.
15. The transistor as claimed in claim 1 , wherein the first and second sections of the first nanowire are narrower than the source and the drain.
16. The transistor as claimed in claim 1 , wherein gate electrode is above and below the first section.
17. The transistor as claimed in claim 1 , wherein sidewalls of the second section of the first nanowire contact the source and the drain.