Frontside to backside signal via in edge cell
A semiconductor device including a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is only in an edge cell of the logic block. A method including forming a logic block, the logic block includes circuitry for one logic function of a semiconductor device, the logic block comprises a set of circuit rows, and edge cells surrounding the logic block, forming a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, where the frontside to backside signal via is in an edge cell of the logic block.
1 . A semiconductor device comprising:
a logic block, wherein the logic block comprises circuitry for one logic function of the semiconductor device;
a double diffusion break region arranged between a first nanosheet transistor device and a second nanosheet transistor device of the logic block, wherein a first gate structure of the first nanosheet transistor device surrounds a top surface, a bottom surface and an end surface of first channel nanosheets in the double diffusion break region, and a second gate structure of the second nanosheet transistor device surrounds a top surface, a bottom surface and an end surface of second channel nanosheets in the double diffusion break region; and
a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, wherein the frontside to backside signal via passes through the double diffusion break region directly between the first gate structure and the second gate structure, wherein the frontside to backside signal via is only in an edge cell of the logic block.
2 . The semiconductor device according to claim 1 , wherein the logic block comprises a set of circuit rows, a set of backside metal Vdd power rails, a set of backside metal Vss power rails.
3 . The semiconductor device according to claim 2 , further comprising:
each backside metal Vdd power rail of the set of backside metal Vdd power rails is continuous with no breaks across the logic block; and
each backside metal Vss power rail of the set of backside metal Vss power rails is continuous with no breaks across the logic block.
4 . The semiconductor device according to claim 1 , wherein the frontside to backside signal via is a nano through silicon via (nTSV).
5 . The semiconductor device according to claim 1 , further comprising:
the logic block comprises circuitry for a microprocessor device.
6 . The semiconductor device according to claim 2 , wherein the set of circuit rows comprises 1000 circuit rows.
7 . The semiconductor device according to claim 1 , further comprising:
a set of front side Vdd power rails and a set of front side Vss power rails.
8 . A method comprising:
forming a logic block, wherein the logic block comprises circuitry for one logic function of a semiconductor device,
wherein the logic block comprises a set of circuit rows, a set of backside metal Vdd power rails, a set of backside metal Vss power rails, and first edge cells arranged along a perimeter of the logic block;
forming a double diffusion break region between a first nanosheet transistor device and a second nanosheet transistor device of the logic block, wherein a first gate structure of the first nanosheet transistor device wraps around ends of first channel nanosheets in the double diffusion break region, and a second gate structure of the second nanosheet transistor device wraps around ends of second channel nanosheets in the double diffusion break region; and
forming a frontside to backside signal via vertically aligned and directly connecting a first backside metal signal to a first frontside metal signal, wherein the frontside to backside signal via passes through the double diffusion break region directly between the first gate structure and the second gate structure, wherein the frontside to backside signal via is within the first edge cells.
9 . The method according to claim 8 , further comprising:
forming a macro cell within the logic block, wherein the macro cell comprises second edge cells arranged along a perimeter of the macro cell, wherein both the macro cell and the second edge cells are within the perimeter of the logic block; and
forming a second frontside to backside signal via vertically aligned and directly connecting a second backside metal signal to a second frontside metal signal, wherein the second frontside to backside signal via is only within one of the second edge cells.
10 . The method according to claim 9 , wherein the logic block comprises a set of circuit rows, wherein at least one circuit row of the set of circuit rows is interrupted by the macro cell.