IP Library Granted Patent US 12,199,041
Granted Patent B2
US 12,199,041 · App. 18/193,977 · Granted Jan 14, 2025

Thinned semiconductor package and related methods

Inventors: Yusheng Lin (Phoenix, AZ); Takashi Noma (Ota, JP); Francis J. Carney (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/53233H01L24/11H01L24/33
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Quick Facts
Patent No.
US 12,199,041
App. No.
18/193,977
Granted
Jan 14, 2025
Kind
B2
Abstract

Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

Claims (39)

1. A semiconductor package comprising:

a die having a first side and a second side opposite the first side;

a first metal layer coupled over a second metal layer, the second metal layer coupled over the first side of the die;

a backside metal layer coupled to the second side of the die;

a mold compound coupled to the die, wherein the mold compound covers a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the second metal layer;

wherein a surface of the mold compound is coplanar with a surface of the first metal layer; and

wherein a portion of the mold compound extends to the second side of the die.

2. The semiconductor package of claim 1 , wherein a third side, a fourth side, a fifth side, and a sixth side of the die are covered by the mold compound.

3. The semiconductor package of claim 1 , wherein the backside metal layer contacts the mold compound.

4. The semiconductor package of claim 1 , wherein the backside metal layer comprises a metal alloy comprising titanium, nickel, silver, vanadium, copper, and any combination thereof.

5. The semiconductor package of claim 1 , wherein the backside metal layer comprises at least three layers.

6. The semiconductor package of claim 5 , wherein each of the at least three layers comprise one of titanium, nickel, silver, vanadium or copper.

7. The semiconductor package of claim 1 , wherein the portion of the mold compound that extends to the second side of the die is a separate mold compound from the mold compound that is coplanar with the surface of the first metal layer.

8. A semiconductor package comprising:

a die having a first side and a second side opposite the first side;

a plurality of bumps, each bump of the plurality of bumps comprising:

a first metal layer coupled to a second metal layer, the second metal layer coupled to the first side of the die; and

a backside metal layer coupled to the second side of the die; and

a mold compound coupled to the die, wherein the mold compound covers a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the second metal layer;

wherein the mold compound covers a first side and a second side of each bump of the plurality of bumps.

9. The semiconductor package of claim 8 , wherein a third side, a fourth side, a fifth side, and a sixth side of the die are covered by the mold compound.

10. The semiconductor package of claim 8 , wherein the backside metal layer comprises copper.

11. The semiconductor package of claim 8 , wherein the backside metal layer comprises a metal alloy comprising titanium, nickel, silver, vanadium, copper, and any combination thereof.

12. The semiconductor package of claim 8 , wherein the backside metal layer comprises at least three layers.

13. The semiconductor package of claim 12 , wherein each of the at least three layers comprise one of titanium, nickel, silver, vanadium or copper.

14. The semiconductor package of claim 8 , wherein a portion of the mold compound extends to the second side of the die and the portion is a separate mold compound from the mold compound that covers the first side and the second side of each bump of the plurality of bumps.

15. A semiconductor package comprising:

a die having a first side and a second side opposite the first side;

a first metal layer coupled to a second metal layer, the second metal layer coupled with the first side of the die;

a third metal layer coupled to the first metal layer;

a backside metal layer coupled to the second side of the die;

a mold compound coupled to the die, wherein the mold compound covers a plurality of sidewalls of the first metal layer, a plurality of sidewalls of the second metal layer, and a plurality of sidewalls of the third metal layer;

wherein a surface of the mold compound is coplanar with a surface of the third metal layer; and

wherein a portion of the mold compound extends to the second side of the die.

16. The semiconductor package of claim 15 , wherein the backside metal layer is directly coupled to the mold compound.

17. The semiconductor package of claim 15 , wherein the backside metal layer comprises a metal alloy comprising titanium, nickel, silver, vanadium, copper, and any combination thereof.

18. The semiconductor package of claim 15 , wherein the backside metal layer comprises at least three layers.

19. The semiconductor package of claim 18 , wherein each of the at least three layers comprise one of titanium, nickel, silver, vanadium or copper.

20. The semiconductor package of claim 15 , wherein the mold compound comprises two separate mold compounds.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 064502, FRAME 0293 Recorded Nov 14, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 065566/0488 →
SECURITY INTEREST Recorded May 9, 2023
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 065402/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2023
From: LIN, YUSHENG; CARNEY, FRANCIS J.; NOMA, TAKASHI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 063188/0665 →
Continuity (3)
Continuation 16941231 · Jul 28, 2020
Division 15921898 · Mar 15, 2018
Related Publication 20230238327A1 · Jul 27, 2023
References Cited (13)
US 7682874B2 · Xiaochun et al. · 2010 [cited by applicant]
US 7745261B2 · Xiochun et al. · 2010 [cited by applicant]
US 8836146B2 · Chou et al. · 2014 [cited by applicant]
US 9147649B2 · Landau · 2015 [cited by examiner]
US 11646267B2 · Lin · 2023 [cited by examiner]
US 20030047339A1 · Lutz · 2003 [cited by applicant]
US 20030116840A1 · Hacke et al. · 2003 [cited by applicant]
US 20030155641A1 · Yeo et al. · 2003 [cited by applicant]
US 20060046436A1 · Ohuchi et al. · 2006 [cited by applicant]
US 20070090496A1 · Otremba · 2007 [cited by examiner]
US 20120104580A1 · Feng et al. · 2012 [cited by applicant]
US 20130037935A1 · Xue et al. · 2013 [cited by applicant]
US 20130210215A1 · Xue et al. · 2013 [cited by applicant]