Forming nanosheet transistor using sacrificial spacer and inner spacers
Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.
1. A method of forming an integrated circuit, the method comprising:
providing a nanosheet structure comprising:
alternating sacrificial and channel nanosheet layers in a nanosheet stack disposed on a dielectric isolation layer;
a gate structure disposed over the nanosheet stack; and
source/drain regions disposed on opposite sides of the nanosheet stack, wherein the source/drain regions contact:
ends of each of the channel nanosheet layers; and
first inner spacers disposed at ends of each of the sacrificial nanosheet layers;
etching to remove the first inner spacers and to define cavities between the sacrificial nanosheet layers and the source/drain regions;
etching to expand the cavities defined between the sacrificial nanosheet layers and the source/drain regions; and
forming second inner spacers in the expanded cavities.
2. The method of claim 1 , wherein the etching to expand the cavities comprises: etching ends of the sacrificial nanosheet layers to expand the cavities defined between the sacrificial nanosheet layers and the source/drain regions.
3. The method of claim 2 , wherein the etching to remove the ends of the sacrificial nanosheet layers comprises laterally etching the ends of the sacrificial nanosheet layers.
4. The method of claim 2 , wherein the ends of the sacrificial nanosheet layers are etched selective to the dielectric isolation layer.
5. The method of claim 2 , wherein the ends of the sacrificial nanosheet layers are etched selective to the channel nanosheet layers.
6. The method of claim 1 , wherein the etching to expand the cavities comprises: etching to remove exposed portions of the source/drain regions.
7. The method of claim 6 , wherein the etching to remove the exposed portions of the source/drain regions comprises: laterally etching the exposed portions of the source/drain regions.
8. The method of claim 1 , wherein exposed portions of the source/drain regions are etched selective to the dielectric isolation layer.
9. The method of claim 1 , wherein exposed portions of the source/drain regions are etched selective to the channel nanosheet layers.
10. The method of claim 1 , wherein the dielectric isolation layer is disposed below the nanosheet stack and the source/drain regions.
11. The method of claim 10 , wherein the dielectric isolation layer disposed below the nanosheet stack and the source/drain regions is contiguous.
12. The method of claim 1 , wherein the sacrificial nanosheet layers comprise SiGe.
13. The method of claim 1 , wherein the second inner spacers comprise a low-K material.
14. The method of claim 1 , wherein the second inner spacers comprise SiBCN.
15. The method of claim 1 , wherein the channel nanosheet layers consist substantially of silicon.
16. The method of claim 1 , further comprising: replacing the sacrificial nanosheet layers and a portion of the gate structure with materials to form a high-K metal gate.
17. The method of claim 16 , wherein the materials to form the high-K metal gate comprise one or more work function metals.
18. The method of claim 16 , wherein a portion of the high-K metal gate disposed above an uppermost channel nanosheet layer extends a greater vertical distance than portions of the high-K metal gate disposed between channel nanosheet layers.
19. The method of claim 18 , further comprising: an uppermost spacer formed on vertical sidewalls of the portion of the high-K metal gate disposed above the uppermost channel nanosheet layer.
20. The method of claim 19 , wherein the uppermost spacer is formed concurrently with the second inner spacers.