IP Library Granted Patent US 12,058,851
Granted Patent B2
US 12,058,851 · App. 18/199,346 · Granted Aug 6, 2024

Method of forming semiconductor memory device

Inventors: Yi-Wei Chen (Taichung, TW); Hsu-Yang Wang (Tainan, TW); Chun-Chieh Chiu (Keelung, TW); Shih-Fang Tzou (Tainan, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H10B12/485H01L21/76804H01L21/76805H01L21/76814H01L21/76819H01L21/76895H10B12/053H10B12/482
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Quick Facts
Patent No.
US 12,058,851
App. No.
18/199,346
Granted
Aug 6, 2024
Kind
B2
Abstract

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Claims (14)

1. A method of forming a semiconductor memory device, comprising:

providing a substrate;

forming a plurality of gates in the substrate, extending along a first direction;

forming a semiconductor layer on the substrate, covering the gates;

forming a protection layer on the semiconductor layer;

forming a plug in the semiconductor layer, between two adjacent gates,

wherein the forming of the plug comprises:

forming a plug hole in the semiconductor layer;

forming a conductive layer on the semiconductor layer to fill in the plug hole having a lower sunken top surface above the plug hole;

performing an etching process to remove the conductive layer on the semiconductor layer till a peripheral top surface of the conductive layer is level with atop surface of the protection layer;

removing the protection layer, wherein a peripheral top surface of the plug is protruded from the top surface of the semiconductor layer creating a tapered protrusion, and the tapered protrusion not directly contacts the semiconductor layer to form the plug;

performing a mechanical polishing process to remove the tapered protrusion of the plug to form a planar top surface of the plug flush with a top surface of the semiconductor layer;

performing a deposition process to from a stacked structure on the top surface of the semiconductor layer and the top surface of the plug; and

patterning the stacked structure to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Priority Claims (1)
CN 201810425155 · May 7, 2018 · national
Continuity (3)
Division 17161685 · Jan 29, 2021
Division 16001949 · Jun 7, 2018
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