Integrated mixed-signal ASIC with ADC, DAC, and DSP
An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
1. An integrated analog to digital converting and digital to analog converting (ADDA) radio frequency (RF) transceiver for satellite applications, the RF transceiver being contained on one or more die, all located on the same package, the RF transceiver comprising:
a plurality of high speed analog to digital conversion (ADC) units, each configured for conversion of an analog RF input signal to a sampled digital signal;
a plurality of high speed digital to analog conversion (DAC) units, each configured for conversion of processed digital data to an analog RF output signal;
a plurality of digital inputs;
a plurality of digital outputs;
one or more first digital signal processing (DSP) cores configured to process data from a high speed ADC unit of the plurality of high speed ADC units and output the processed data to a digital output of the plurality of digital outputs; and
one or more second digital signal processing (DSP) cores configured to process data from a digital input of the plurality of digital inputs and output the processed data to a high speed DAC unit of the plurality of high speed DAC units;
wherein the RF transceiver is configured to mitigate Single Event Effect (SEE) induced events with a duration less than 1 nanosecond (ns).
2. The RF transceiver of claim 1 , wherein the RF transceiver is further configured to mitigate the SEE induced events with a duration less than 100 picoseconds (ps).
3. The RF transceiver of claim 1 , wherein the provision of the RF transceiver located on the same package enables mitigation of the SEE induced events less than 1 ns.
4. The RF transceiver of claim 1 , wherein the RF transceiver is further configured to power off one or more of the high speed ADC units while one or more of the other high speed ADC units are powered on.
5. The RF transceiver of claim 1 , wherein the RF transceiver is further configured to power off one or more of the high speed DAC units while one or more of the other high speed DAC units are powered on.
6. The RF transceiver of claim 1 , wherein the high speed ADC units, the high speed DAC units, and the one or more first and second DSP cores are fabricated via a semiconductor process with a feature size in the range of 10 nanometer (nm) to 45 nm.
7. The RF transceiver of claim 1 , wherein the RF transceiver is further configured to perform direct conversion, downconversion, or upconversion of RF signals up to 30 GHz.
8. The RF transceiver of claim 1 , further comprising:
a router for routing beamformed subchannel data from the high speed ADC units.
9. The RF transceiver of claim 1 , further comprising:
a plurality of Serializer/Deserializer (SerDes) lanes comprising signal lines, wherein one or more of the high speed ADC units, the high speed DAC units, and the one or more first and second DSP cores are connected via the signal lines.
10. The RF transceiver of claim 1 , wherein one or more of the high speed ADC units, the high speed DAC units, the plurality of digital inputs, the plurality of digital outputs, the first DSP cores, and the second DSP cores are radiation hardened by process or radiation hardened by design.
11. The RF transceiver of claim 1 , wherein the RF transceiver is fabricated via silicon on insulator technology.
12. The RF transceiver of claim 1 , wherein the RF transceiver has a single event effect cross-section of less than or equal to 10 −4 cm 2 at a linear energy transfer greater than or equal to 37 MeV cm 2 /mg (mega electron Volt-square centimeter per milligram).
13. The RF transceiver of claim 1 , wherein the RF transceiver is further configured to cause the high speed ADC units to become non-operational and cause the high speed DAC units, the plurality of digital inputs, the plurality of digital outputs, and the one or more first and second DSP cores to become operational.
14. The RF transceiver of claim 1 , wherein the RF transceiver is further configured to cause the high speed DAC units to become non-operational and cause the high speed ADC units, the plurality of digital inputs, the plurality of digital outputs, and the one or more first and second DSP cores to become operational.
15. The RF transceiver of claim 1 , wherein the high speed ADC units or the high speed DAC units of the RF transceiver are caused to become non-operational by power islanding or clock gating.