Transmission gate circuit, inverter circuit and gate driving circuit including the same
A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.
1. A gate driving circuit comprising a plurality of stages, wherein each of the plurality of stages comprises:
a signal transmission unit connected between an input terminal to which a start signal is configured to be applied and a first node, and configured to transmit, to the first node, the start signal according to a clock signal;
a first inverter configured to control a voltage level of a second node according to a voltage level of the first node; and
a second inverter configured to output an output signal of a first voltage of a first voltage level or a second voltage of a second voltage level according to the voltage level of the second node,
wherein the second inverter comprises:
a first pull-up transistor connected between a first voltage input terminal and an output terminal, and comprising a gate connected to the second node, the first voltage input terminal configured to supply the first voltage;
a first pull-down transistor connected between a second voltage input terminal and the output terminal, and comprising a first gate connected to the second node and a second gate connected to a first control node, the second voltage input terminal configured to supply the second voltage;
a first capacitor connected between the first gate of the first pull-down transistor and the first control node; and
a first control transistor connected between the first control node and a ground terminal and comprising a gate connected to the ground terminal.
2. The gate driving circuit of claim 1 , wherein the first pull-down transistor is an N-channel oxide transistor.
3. The gate driving circuit of claim 2 , wherein the first gate of the first pull-down transistor is a top gate above a semiconductor layer, and the second gate of the first pull-down transistor is a bottom gate under the semiconductor layer.
4. The gate driving circuit of claim 1 , wherein the first inverter comprises:
a second pull-up transistor connected between the first voltage input terminal and the second node and comprising a gate connected to the first node;
a second pull-down transistor connected between the second voltage input terminal and the second node and comprising a first gate connected to the first node and a second gate connected to a second control node;
a second capacitor connected between the first gate of the second pull-down transistor and the second control node; and
a second control transistor connected between the second control node and the ground terminal and comprising a gate connected to the ground terminal.
5. The gate driving circuit of claim 4 , wherein the second pull-down transistor is an N-channel oxide transistor.
6. The gate driving circuit of claim 5 , wherein the first gate of the second pull-down transistor is a top gate above a semiconductor layer, and the second gate of the second pull-down transistor is a bottom gate under the semiconductor layer.
7. The gate driving circuit of claim 1 , wherein the signal transmission unit comprises:
a first transistor connected between the input terminal and the first node and comprising a gate connected to a second clock terminal;
a second transistor connected between the input terminal and the first node and comprising a first gate connected to a first clock terminal and a second gate connected to a third control node;
a third capacitor connected between the first gate of the second transistor and the third control node; and
a third control transistor connected between the third control node and the ground terminal and comprising a gate connected to the ground terminal.
8. The gate driving circuit of claim 7 , wherein a second clock signal configured to be applied to the second clock terminal is an inverted signal of a first clock signal configured to be applied to the first clock terminal.
9. The gate driving circuit of claim 7 , wherein the second transistor is an N-channel oxide transistor.
10. The gate driving circuit of claim 7 , wherein the first gate of the second transistor is a top gate above a semiconductor layer, and the second gate of the second transistor is a bottom gate under the semiconductor layer.
11. The gate driving circuit of claim 1 , further comprising a fourth capacitor connected between the first node and a third voltage supply terminal.
12. The gate driving circuit of claim 11 , wherein the third voltage supply terminal is the ground terminal.
13. The gate driving circuit of claim 11 , wherein the third voltage supply terminal is configured to receive the first voltage or the second voltage.
14. The gate driving circuit of claim 1 , wherein the first pull-up transistor comprises a plurality of sub-transistors connected in parallel between the first voltage input terminal and the output terminal.
15. The gate driving circuit of claim 1 , wherein the start signal is an output signal configured to be output from a previous stage.
16. A transmission gate circuit comprising:
a first transistor connected between an input terminal and an output terminal and comprising a gate connected to a second clock terminal;
a second transistor connected between the input terminal and the output terminal and comprising a first gate connected to a first clock terminal and a second gate connected to a control node;
a capacitor connected between the first gate of the second transistor and the control node; and
a third transistor connected between the control node and a ground terminal and comprising a gate connected to the ground terminal.
17. The transmission gate circuit of claim 16 , wherein a second clock signal configured to be applied to the second clock terminal is an inverted signal of a first clock signal configured to be applied to the first clock terminal.
18. The transmission gate circuit of claim 16 , wherein the second transistor is an N-channel oxide transistor.
19. An inverter circuit comprising:
a first transistor connected between a first voltage input terminal to which a first voltage of a first voltage level is configured to be applied and an output terminal, and comprising a gate connected to an input terminal;
a second transistor connected between a second voltage input terminal to which a second voltage of a second voltage level is configured to be applied and the output terminal, and comprising a first gate connected to the input terminal and a second gate connected to a control node;
a capacitor connected between the first gate of the second transistor and the control node; and
a third transistor connected between the control node and a ground terminal and comprising a gate connected to the ground terminal.
20. The inverter circuit of claim 19 , wherein the second transistor is an N-channel oxide transistor.
21. A gate driving circuit comprising:
a transmission circuit configured to receive a clock signal and an inverted clock signal and transmit an input signal to a first node; and
an inverter circuit configured to receive a first reference voltage and a second reference voltage and invert and output a voltage level of a voltage of the first node,
wherein each of the transmission circuit and the inverter circuit comprises a P-channel transistor and an N-channel transistor,
wherein the transmission circuit comprises:
a first transistor connected between an input terminal and the first node, and comprising a gate connected to a second clock terminal to which the inverted clock signal is configured to be supplied;
a second transistor connected between the input terminal and the first node, and comprising a first gate connected to a first clock terminal to which the clock signal is configured to be supplied and a second gate connected to a first control node;
a first capacitor connected between the first gate of the second transistor and the first control node; and
a first control transistor connected between the first control node and a ground terminal and comprising a gate connected to the ground terminal,
wherein the second transistor is an N-channel transistor.
22. The gate driving circuit of claim 21 , wherein the inverter circuit comprises:
a first inverter configured to invert a voltage level of a voltage of the first node and output a voltage of the inverted voltage level to a second node; and
a second inverter configured to invert a voltage level of a voltage of the second node and output a voltage of the inverted voltage level to an output terminal.
23. The gate driving circuit of claim 21 , further comprising a fourth capacitor connected between the first node and a third voltage supply terminal.
24. A gate driving circuit comprising:
a transmission circuit configured to receive a clock signal and an inverted clock signal and transmit an input signal to a first node; and
an inverter circuit configured to receive a first reference voltage and a second reference voltage and invert and output a voltage level of a voltage of the first node,
wherein each of the transmission circuit and the inverter circuit comprises a P-channel transistor and an N-channel transistor,
wherein the inverter circuit comprises:
a first inverter configured to invert a voltage level of a voltage of the first node and output a voltage of the inverted voltage level to a second node; and
a second inverter configured to invert a voltage level of a voltage of the second node and output a voltage of the inverted voltage level to an output terminal, wherein the first inverter comprises:
a fourth transistor connected between a first voltage input terminal configured to supply the first reference voltage and the second node, and comprising a gate connected to the first node;
a fifth transistor connected between a second voltage input terminal configured to supply the second reference voltage and the second node, and comprising a first gate connected to the first node and a second gate connected to a second control node;
a second capacitor connected between the first gate of the fifth transistor and the second control node; and
a sixth transistor connected between the second control node and a ground terminal and comprising a gate connected to the ground terminal,
wherein the fifth transistor is an N-channel transistor.
25. A gate driving circuit comprising:
a transmission circuit configured to receive a clock signal and an inverted clock signal and transmit an input signal to a first node; and
an inverter circuit configured to receive a first reference voltage and a second reference voltage and invert and output a voltage level of a voltage of the first node,
wherein each of the transmission circuit and the inverter circuit comprises a P-channel transistor and an N-channel transistor,
wherein the inverter circuit comprises:
a first inverter configured to invert a voltage level of a voltage of the first node and output a voltage of the inverted voltage level to a second node; and
a second inverter configured to invert a voltage level of a voltage of the second node and output a voltage of the inverted voltage level to an output terminal, wherein the second inverter comprises:
a seventh transistor connected between a first voltage input terminal configured to supply the first reference voltage and the output terminal, and comprising a gate connected to the second node;
an eighth transistor connected between a second voltage input terminal configured to supply the second reference voltage and the output terminal, and comprising a first gate connected to the second node and a second gate connected to a third control node;
a third capacitor connected between the first gate of the eighth transistor and the third control node; and
a ninth transistor connected between the third control node and a ground terminal and comprising a gate connected to the ground terminal,
wherein the eighth transistor is an N-channel transistor.