Automation methods for 3D integrated circuits and devices
A method of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level; levels connection pads between the first level and the second level; providing placement data of the second level; performing a placement of the first level using a placer executed by a computer, where the placement of the first level is based on the placement of the levels connection pads, where the placer is part of a Computer Aided Design (CAD) tool, where the first level includes first routing layers; performing a routing of the first level by routing layers using a router executed by a computer, where the router is a part of the CAD tool or a part of another CAD tool, where at least one metal routing layer is in-between the first level first transistors and the second level second transistors.
1. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level,
wherein said first level comprises a plurality of first transistors,
wherein said second level comprises a plurality of second transistors, and
wherein said second level is disposed on top of said first level;
levels connection pads between said first level and said second level;
providing placement data of said second level;
performing placement of said levels connection pads based on said placement data,
performing a placement of said first level using a placer program executed by a computer,
wherein said placement of said first level is based on said placement of said levels connection pads,
wherein said placer is part of a Computer Aided Design (CAD) tool, and
wherein said first level comprises first routing layers; and
performing a routing of said first level by routing layers using a router executed by a computer,
wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool, and
wherein at least one metal routing layer is disposed in-between said plurality of first transistors and said plurality of second transistors.
2. The method according to claim 1 ,
wherein a majority area of said second level comprises memory.
3. The method according to claim 1 ,
wherein results of said second level is a generic structure.
4. The method according to claim 1 ,
wherein said first level is designed to be processed with a different process node than a process node used for said second level.
5. The method according to claim 1 , further comprising:
performing a routing of said second level by routing layers using a router executed by a computer.
6. The method according to claim 1 ,
wherein said first level comprises Input and Output cells (“IO”).
7. The method according to claim 1 ,
wherein said second level comprises one or more RF (Radio Frequency) circuits.
8. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level,
wherein said first level comprises a plurality of first transistors,
wherein said second level comprises a plurality of second transistors,
wherein said second level is disposed on top of said first level,
levels connection pads between said first level and said second level;
providing placement data of said second level;
performing placement of said levels connection pads based on said placement data,
performing a placement of said first level using a placer program executed by a computer,
wherein said placement of said first level is based on said placement of said levels connection pads,
wherein said placer is part of a Computer Aided Design (CAD) tool, and
wherein said first level comprises first routing layers; and
performing a routing of said first level by routing layers using a router executed by a computer,
wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool,
wherein at least one metal routing layer is disposed in-between said plurality of first transistors and said plurality of second transistors, and
wherein a majority area of said second level comprises memory.
9. The method according to claim 8 ,
wherein results of said second level is a generic structure.
10. The method according to claim 8 ,
wherein at least one metal routing layer is disposed in-between said plurality of first transistors and said plurality of second transistors.
11. The method according to claim 8 ,
wherein said first level is designed to be processed with a different process node than a process node used for said second level.
12. The method according to claim 8 , further comprising:
performing a routing of said second level by routing layers using a router executed by a computer.
13. The method according to claim 8 ,
wherein said first level comprises Input and Output cells (“IO”).
14. The method according to claim 8 ,
wherein said second level comprises one or more RF (Radio Frequency) circuits.
15. A method of designing a 3D Integrated Circuit, the method comprising:
partitioning at least one design into at least two levels, a first level and a second level,
wherein said first level comprises a plurality of first transistors,
wherein said second level comprises a plurality of second transistors,
wherein said second level is disposed on top of said first level;
levels connection pads between said first level and said second level;
providing placement data of said second level;
performing placement of said levels connection pads based on said placement data,
performing a placement of said first level using a placer program executed by a computer,
wherein said placement of said first level is based on said placement of said levels connection pads,
wherein said placer is part of a Computer Aided Design (CAD) tool, and
wherein said first level comprises first routing layers; and
performing a routing of said first level by routing layers using a router executed by a computer,
wherein said router is a part of the Computer Aided Design (CAD) tool or a part of another CAD tool,
wherein at least one metal routing layer is disposed in-between said plurality of first transistors and said plurality of second transistors, and
wherein said first level is designed to be processed with a different process node than a process node used for said second level.
16. The method according to claim 15 ,
wherein a majority area of said first level comprises logic circuits.
17. The method according to claim 15 ,
wherein results of said second level is a generic structure.
18. The method according to claim 15 , further comprising:
providing placement data of said first level; and
performing a placement of said second level using a placer executed by a computer,
wherein said placement of said second level is based on said placement data.
19. The method according to claim 15 ,
wherein results of said second level is a generic structure.
20. The method according to claim 15 ,
wherein said first level comprises Input and Output cells (“IO”).