IP Library Granted Patent US 12,593,453
Granted Patent B2
US 12,593,453 · App. 18/208,943 · Granted Mar 31, 2026

Ferroelectric memory device

Inventors: Kiheun Lee (Suwon-si, KR); Yongseok Kim (Suwon-si, KR); Hyuncheol Kim (Suwon-si, KR); Daewon Ha (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10B51/20H10B51/10H10D30/701H10D62/84H10D64/689
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Quick Facts
Patent No.
US 12,593,453
App. No.
18/208,943
Granted
Mar 31, 2026
Kind
B2
Abstract

A ferroelectric memory device includes a channel layer, a gate insulation layer on the channel layer, and a gate electrode layer on the gate insulation layer. The gate insulation layer includes a ferroelectric inductive layer and a ferroelectric stack structure on the ferroelectric inductive layer, and the ferroelectric stack structure is stacked in an order or reverse order of a ferroelectric layer and a non-ferroelectric layer.

Claims (39)

1 . A ferroelectric memory device, comprising:

a channel layer;

a gate insulation layer on the channel layer; and

a gate electrode layer on the gate insulation layer, the gate insulation layer including:

a ferroelectric inductive layer, and

a ferroelectric stack structure on the ferroelectric inductive layer, the ferroelectric stack structure including a stack of a ferroelectric layer and a non-ferroelectric layer:

wherein at least one of the ferroelectric inductive layer, the ferroelectric layer or the non-ferroelectric layer includes a two-dimensional material.

2 . The ferroelectric memory device as claimed in claim 1 , wherein the ferroelectric layer includes a two-dimensional transition metal dichalcogenide layer.

3 . The ferroelectric memory device as claimed in claim 2 , wherein the two-dimensional transition metal dichalcogenide layer includes an MX 2 layer having a 3R-type rhombohedral crystal structure, M including one or more of molybdenum (Mo), tungsten (W), and zirconium (Zr), and X including one or more of sulfur(S), selenium (Se), and tellurium (Te).

4 . The ferroelectric memory device as claimed in claim 3 , wherein the non-ferroelectric layer includes a nitride having a hexagonal crystal structure, as a two-dimensional material.

5 . The ferroelectric memory device as claimed in claim 2 , wherein the ferroelectric layer includes a nitride having a hexagonal crystal structure, as a two-dimensional material.

6 . The ferroelectric memory device as claimed in claim 1 , wherein the ferroelectric stack structure includes a plurality of ferroelectric stack structure units, each of the plurality of ferroelectric stack structure units including the stack of the ferroelectric layer and the non-ferroelectric layer.

7 . The ferroelectric memory device as claimed in claim 1 , wherein the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof.

8 . The ferroelectric memory device as claimed in claim 7 , wherein the ferroelectric inductive layer includes a first ferroelectric inductive layer, an oxygen-reactive layer, and a second ferroelectric inductive layer, which are sequentially stacked.

9 . The ferroelectric memory device as claimed in claim 8 , wherein each of the first ferroelectric inductive layer and the second ferroelectric inductive layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof.

10 . The ferroelectric memory device as claimed in claim 8 , wherein the oxygen-reactive layer includes a silicon oxide, the silicon oxide being reactive with oxygen.

11 . The ferroelectric memory device as claimed in claim 8 , further comprising an interface layer between the channel layer and the first ferroelectric inductive layer.

12 . A ferroelectric memory device, comprising:

a channel layer;

a gate insulation layer on the channel layer; and

a gate electrode layer on the gate insulation layer, the gate insulation layer including:

a ferroelectric inductive layer, and

a ferroelectric stack structure on the ferroelectric inductive layer, the ferroelectric stack structure having a stack of a ferroelectric layer and a non-ferroelectric layer and including a two-dimensional transition metal dichalcogenide layer.

13 . The ferroelectric memory device as claimed in claim 12 , wherein the two-dimensional transition metal dichalcogenide layer includes an MX 2 layer having a 3R-type rhombohedral crystal structure, M including one or more of molybdenum (Mo), tungsten (W), and zirconium (Zr), and X including one or more of sulfur(S), selenium (Se), and tellurium (Te).

14 . The ferroelectric memory device as claimed in claim 13 , wherein the non-ferroelectric layer includes a nitride having a hexagonal crystal structure, as a two-dimensional material.

15 . The ferroelectric memory device as claimed in claim 12 , wherein the ferroelectric inductive layer includes a nitride having a hexagonal crystal structure.

16 . The ferroelectric memory device as claimed in claim 12 , wherein the ferroelectric stack structure includes a plurality of ferroelectric stack structure units, each of the plurality of ferroelectric stack structure units including the stack of the ferroelectric layer and the non-ferroelectric layer.

17 . A ferroelectric memory device, comprising:

a channel layer;

a gate insulation layer on the channel layer; and

a gate electrode layer on the gate insulation layer, the gate insulation layer including:

a ferroelectric inductive layer, and

a ferroelectric stack structure on the ferroelectric inductive layer, the ferroelectric stack structure including a stack of a non-ferroelectric layer and a ferroelectric layer,

wherein the ferroelectric inductive layer includes a first ferroelectric inductive layer, an oxygen-reactive layer, and a second ferroelectric inductive layer, which are sequentially stacked.

18 . The ferroelectric memory device as claimed in claim 17 , wherein the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof.

19 . The ferroelectric memory device as claimed in claim 17 , wherein:

each of the first ferroelectric inductive layer and the second ferroelectric inductive layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination thereof, and

the oxygen-reactive layer includes silicon oxide capable of reacting with oxygen.

20 . The ferroelectric memory device as claimed in claim 17 , wherein the ferroelectric stack structure includes a plurality of ferroelectric stack structure units, each of the plurality of ferroelectric stack structure units including the stack of the ferroelectric layer and the non-ferroelectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2023
From: LEE, KIHEUN; KIM, YONGSEOK; KIM, HYUNCHEOL; HA, DAEWON
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 063929/0229 →
Priority Claims (1)
KR 10-2022-0098126 · Aug 5, 2022 · national
Continuity (1)
Related Publication 20240049472A1 · Feb 8, 2024
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