Self-aligned metal compound layers for semiconductor devices
The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.
1. A method for forming a semiconductor device, comprising:
forming a substrate;
forming first and second spacers on the substrate;
depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers;
depositing a layer stack on the substrate and between and in contact with the first and second SAM layers, wherein depositing the layer stack comprises depositing a ferroelectric layer;
removing the first and second SAM layers;
depositing a metal compound layer on the ferroelectric layer, wherein portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers; and
depositing a gate electrode on the metal compound layer and between the first and second spacers.
2. The method of claim 1 , wherein depositing the layer stack further comprises depositing another metal compound layer before depositing the ferroelectric layer.
3. The method of claim 1 , wherein depositing the layer stack further comprises depositing a high-k dielectric layer before depositing the ferroelectric layer.
4. The method of claim 1 , wherein depositing the layer stack further comprises:
depositing an interface layer on the substrate; and
depositing a high-k dielectric layer on the interface layer.
5. The method of claim 1 , wherein depositing the metal compound layer comprises depositing a metal-based oxide material using atomic layer deposition (ALD).
6. The method of claim 1 , wherein depositing the metal compound layer comprises:
depositing a metal compound material; and
performing an etch back process on the metal compound material.
7. The method of claim 1 , further comprising performing a cleaning process on the substrate prior to depositing the first and second SAM layers.
8. The method of claim 1 , wherein depositing the first and second SAM layers comprises depositing graphene.
9. The method of claim 1 , wherein depositing the metal compound layer comprises depositing a metal compound material on the substrate and sidewalls of the ferroelectric layer.
10. The method of claim 1 , wherein depositing the metal compound layer further comprises depositing a metal compound material on sidewalls of the layer stack.
11. A method for forming a semiconductor device, comprising:
forming a fin;
forming a spacer on the fin;
depositing a self-assembly (SAM) layer on a sidewall of the spacer and over a portion of the fin;
depositing a layer stack on the fin and in contact with the SAM layer;
removing the SAM layer and exposing the portion of the fin;
forming a first portion of a metal compound layer between the layer stack and the sidewall of the spacer, wherein the first portion is in contact with the layer stack and the sidewall of the spacer;
forming a second portion of the metal compound layer on a top surface of the layer stack; and
depositing a gate electrode on the first and second portions of the metal compound layer.
12. The method of claim 11 , wherein depositing the layer stack comprises depositing a ferroelectric layer.
13. The method of claim 11 , wherein forming the first portion of the metal compound layer comprises depositing a metal compound material on the portion of the fin.
14. The method of claim 11 , wherein depositing the SAM layer comprises depositing graphene.
15. The method of claim 11 , wherein depositing the metal compound layer comprises depositing a metal-based oxide material using atomic layer deposition (ALD).
16. A semiconductor device, comprising:
a fin;
a spacer on the fin;
a layer stack on the fin, the layer stack comprising a ferroelectric layer;
a metal compound layer, comprising:
a first portion in contact with a sidewall of the layer stack and a sidewall of the spacer; and
a second portion on a top surface of the layer stack; and
a gate electrode in contact with the first and second portions of the metal compound layer.
17. The semiconductor device of claim 16 , wherein the layer stack further comprises another metal compound layer.
18. The semiconductor device of claim 16 , wherein the gate electrode is in contact with the spacer.
19. The semiconductor device of claim 16 , wherein the first portion of the metal compound layer extends above a top surface of the second portion of the metal compound layer.
20. The semiconductor device of claim 16 , wherein a thickness of the first portion between the sidewall of the layer stack and the sidewall of the spacer is between about 5 Å and about 10 Å.