Granted Patent
B2
US 12,393,342 · App. 18/211,356 · Granted Aug 19, 2025
Apparatuses and methods for parallel writing to multiple memory device structures
Inventors:
Jason T. Zawodny (Grand Rapids, MI); Glen E. Hush (Boise, ID); Troy A. Manning (Meridian, ID); Timothy P. Finkbeiner (Boise, ID)
G06F3/0611G06F3/0625G06F3/0659G06F3/0683G06F15/7821G11C7/10G11C7/1006G11C8/12G11C29/28G11C5/025G11C2029/2602
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Abstract
The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.
Claims (28)
1. An apparatus, comprising:
an array of memory cells; and
a controller coupled to the array, the controller configured to:
receive, via a component, a command comprising instructions for performing one or more logical operations on data within a plurality of banks of the array of memory cells in parallel, wherein the command is multicast to a subset of controllers of a plurality of controllers, the subset including the controller; and
send the instructions to one or more compute components each associated with respective banks of the plurality of banks to perform, in parallel, the one or more logical operations.
2. The apparatus of claim 1 , wherein the controller is configured to receive the data in association with a processor-in-memory (PIM) calculation to be subsequently performed using the data.
3. The apparatus of claim 1 , wherein the array of memory cells is an array of dynamic random access memory (DRAM) cells.
4. The apparatus of claim 1 , further comprising:
a number of registers indicating addresses corresponding to a plurality of locations to which the data is written.
5. The apparatus of claim 1 , wherein the one or more compute components are configured to perform the one or more logical operations in accordance with the instructions.
6. A system, comprising:
an array of memory cells;
a component configured to generate a multicast command comprising instructions for performing one or more logical operations, in parallel, on data within a plurality of banks of the array of memory cells, wherein the multicast command is multicast to a subset of controllers of a plurality of controllers; and
a controller of the subset of controllers configured to, in response to receiving the multicast command from the component:
send the instructions to one or more compute components each associated with respective banks of the plurality of banks to perform, in parallel, the one or more logical operations.
7. The system of claim 6 , further comprising:
a number of registers configured to store addresses of a plurality of locations to which the data is written.
8. The system of claim 6 , wherein the component comprises a channel controller configured to provide the multicast command to the plurality of controllers.
9. The system of claim 6 , wherein the component is configured to generate the multicast command in association with performing a processor-in-memory (PIM) operation.
10. The system of claim 9 , wherein the data is used to perform the PIM operation.
11. A method, comprising:
receiving, via a component, a command comprising instructions for performing one or more logical operations on data within a plurality of banks of an array of memory cells in parallel, wherein the command is multicast to a subset of controllers of a plurality of controllers; and
sending the instructions to one or more compute components each associated with respective banks of the plurality of banks to perform, in parallel, the one or more logical operations.
12. The method of claim 11 , wherein the method includes receiving the command at respective controllers corresponding to the plurality of banks.
13. The method of claim 11 , wherein the method includes writing the data to at least two different subarrays within at least two different banks of the plurality of banks.
14. The method of claim 11 , wherein the method includes setting registers to indicate a plurality of locations within the plurality of banks to be written in parallel.
15. The method of claim 11 , wherein the method includes receiving the command from a host.
16. The method of claim 11 , wherein the method includes receiving the command from a channel controller.
Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded Oct 25, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 069026/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded Jun 19, 2023
From: ZAWODNY, JASON T.; HUSH, GLEN E.; MANNING, TROY A.; FINKBEINER, TIMOTHY P.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 063984/0701 →
Continuity (6)
Continuation
PCTUS2016015029
· Jan 27, 2016
Provisional Application
62112868
· Feb 6, 2015
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