Granted Patent B2

US 12,445,542 · App. 18/212,546 · Granted Oct 14, 2025

Inventor: Patrick Bosshart (Plano, TX)

Assignee: Barefoot Networks, Inc.

H04L69/22H04L49/3009

Abstract

Claims (142)

1. Integrated circuit for use in packet switching-related operations in a network, the integrated circuit being configurable to be used in a hardware switch in association with ternary content addressable memory (TCAM), the packet switching-related operations being programmable based upon configuration data to be received by the integrated circuit, the integrated circuit comprising:

an ingress pipeline to process packet data received by the integrated circuit;

a shared queuing system to queue the packet data processed by the ingress pipeline; and

an egress pipeline to obtain, from the shared queuing system, the packet data processed by the ingress pipeline, and also to further process the packet data processed by the ingress pipeline;

wherein:

the ingress pipeline comprises a configurable parser and configurable match-action stages;

the egress pipeline comprises at least one other stage;

the configurable parser is to be configured, in accordance with the configuration data, to parse packet header fields to generate multiple sets of header field data;

the multiple sets of header field data comprise (1) at least one set of header field data for use by at least one of the match-action stages and (2) at least one other set of header field data;

the at least one of the match-action stages is to perform actions associated with at least certain portions of the at least one set of header field data;

the at least one of the match-action stages is to determine the actions based upon matching, at least in part, of the at least one set of header field data with match table data;

the match action table data is configurable to comprise both (1) ternary content addressable table data to be stored in the TCAM and (2) exact match table data;

the actions and the match action table data are to be configured based upon the configuration data;

the actions are configurable to comprise packet header data modification and/or packet data port assignment;

the at least one other stage is to generate output packet data for output from the integrated circuit;

the at least one other stage is to generate the output packet data based upon modified packet header data generated by the at least one of the match-action stages;

the at least one other set of header field data is unavailable for match-action stage modification; and

the parser is configurable, based upon the configuration data, to store the at least one set of header field data, at least in part, in containers of different sizes.

2. The integrated circuit of claim 1 , wherein:

the parser is to extract the at least one set of header field data and the at least one other set of header field data in accordance with parse graph data that defines manner of header field extraction in terms of current bit field and next bit field for extraction; and

the parse graph data is to be defined by the configuration data.

3. The integrated circuit of claim 2 , wherein:

the configuration data is to be generated by a compiler based upon user-written code; and

the compiler is not part of the integrated circuit.

4. The integrated circuit of claim 3 , wherein:

the actions are also configurable to comprise:

address modification; and

packet data drop; and

the packet switching-related operations are configurable to comprise:

multi-layer tunneling protocol processing;

GENEVE/GRE protocol processing; and

variable field processing.

5. The integrated circuit of claim 4 , wherein:

the configuration data is configurable to instruct the parser to determine when header end has been reached, and to stop parse graph traversal and header parsing.

6. At least one non-transitory machine-readable storage medium storing instructions for being executed by an integrated circuit, the integrated circuit being for use in packet switching-related operations in a network, the integrated circuit being configurable to be used in a hardware switch in association with ternary content addressable memory (TCAM), the packet switching-related operations being programmable based upon configuration data to be received by the integrated circuit, the instructions when executed by the integrated circuit resulting in the integrated circuit being configured to perform operations comprising:

processing, by an ingress pipeline of the integrated circuit, packet data received by the integrated circuit;

queuing, by a shared queuing system of the integrated circuit, the packet data processed by the ingress pipeline; and

obtaining, by an egress pipeline of the integrated circuit, from the shared queuing system, the packet data processed by the ingress pipeline; and

further processing, by the egress pipeline, the packet data processed by the ingress pipeline;

wherein:

the ingress pipeline comprises a configurable parser and configurable match-action stages;

the egress pipeline comprises at least one other stage;

the configurable parser is to be configured, in accordance with the configuration data, to parse packet header fields to generate multiple sets of header field data;

the multiple sets of header field data comprise (1) at least one set of header field data for use by at least one of the match-action stages and (2) at least one other set of header field data;

the at least one of the match-action stages is to perform actions associated with at least certain portions of the at least one set of header field data;

the at least one of the match-action stages is to determine the actions based upon matching, at least in part, of the at least one set of header field data with match table data;

the match action table data is configurable to comprise both (1) ternary content addressable table data to be stored in the TCAM and (2) exact match table data;

the actions and the match action table data are to be configured based upon the configuration data;

the actions are configurable to comprise packet header data modification and/or packet data port assignment;

the at least one other stage is to generate output packet data for output from the integrated circuit;

the at least one other stage is to generate the output packet data based upon modified packet header data generated by the at least one of the match-action stages;

the at least one other set of header field data is unavailable for match-action stage modification; and

the parser is configurable, based upon the configuration data, to store the at least one set of header field data, at least in part, in containers of different sizes.

7. The at least one non-transitory machine-readable storage medium of claim 6 , wherein:

the parser is to extract the at least one set of header field data and the at least one other set of header field data in accordance with parse graph data that defines manner of header field extraction in terms of current bit field and next bit field for extraction; and

the parse graph data is to be defined by the configuration data.

8. The at least one non-transitory machine-readable storage medium of claim 7 , wherein:

the configuration data is to be generated by a compiler based upon user-written code; and

the compiler is not part of the integrated circuit.

9. The at least one non-transitory machine-readable storage medium of claim 8 , wherein:

the actions are also configurable to comprise:

address modification; and

packet data drop; and

the packet switching-related operations are configurable to comprise:

multi-layer tunneling protocol processing;

GENEVE/GRE protocol processing; and

variable field processing.

10. The at least one non-transitory machine-readable storage medium of claim 9 , wherein:

the configuration data is configurable to instruct the parser to determine when header end has been reached, and to stop parse graph traversal and header parsing.

11. A method implemented using an integrated circuit, the integrated circuit being for use in packet switching-related operations in a network, the integrated circuit being configurable to be used in a hardware switch in association with ternary content addressable memory (TCAM), the packet switching-related operations being programmable based upon configuration data to be received by the integrated circuit, the method comprising:

processing, by an ingress pipeline of the integrated circuit, packet data received by the integrated circuit;

queuing, by a shared queuing system of the integrated circuit, the packet data processed by the ingress pipeline; and

obtaining, by an egress pipeline of the integrated circuit, from the shared queuing system, the packet data processed by the ingress pipeline; and

further processing, by the egress pipeline, the packet data processed by the ingress pipeline;

wherein:

the ingress pipeline comprises a configurable parser and configurable match-action stages;

the egress pipeline comprises at least one other stage;

the configurable parser is to be configured, in accordance with the configuration data, to parse packet header fields to generate multiple sets of header field data;

the multiple sets of header field data comprise (1) at least one set of header field data for use by at least one of the match-action stages and (2) at least one other set of header field data;

the at least one of the match-action stages is to perform actions associated with at least certain portions of the at least one set of header field data;

the at least one of the match-action stages is to determine the actions based upon matching, at least in part, of the at least one set of header field data with match table data;

the match action table data is configurable to comprise both (1) ternary content addressable table data to be stored in the TCAM and (2) exact match table data;

the actions and the match action table data are to be configured based upon the configuration data;

the actions are configurable to comprise packet header data modification and/or packet data port assignment;

the at least one other stage is to generate output packet data for output from the integrated circuit;

the at least one other stage is to generate the output packet data based upon modified packet header data generated by the at least one of the match-action stages;

the at least one other set of header field data is unavailable for match-action stage modification; and

the parser is configurable, based upon the configuration data, to store the at least one set of header field data, at least in part, in containers of different sizes.

12. The method of claim 11 , wherein:

the parser is to extract the at least one set of header field data and the at least one other set of header field data in accordance with parse graph data that defines manner of header field extraction in terms of current bit field and next bit field for extraction; and

the parse graph data is to be defined by the configuration data.

13. The method of claim 12 , wherein:

the configuration data is to be generated by a compiler based upon user-written code; and

the compiler is not part of the integrated circuit.

14. The method of claim 13 , wherein:

the actions are also configurable to comprise:

address modification; and

packet data drop; and

the packet switching-related operations are configurable to comprise:

multi-layer tunneling protocol processing;

GENEVE/GRE protocol processing; and

variable field processing.

15. The method of claim 14 , wherein:

the configuration data is configurable to instruct the parser to determine when header end has been reached, and to stop parse graph traversal and header parsing.

16. A hardware switch configurable to be used in association with ternary content addressable memory (TCAM), the hardware switch being for use in a network, the hardware switch comprising:

ingress ports;

egress ports; and

an integrated circuit coupled to both the ingress ports and the egress ports, the integrated circuit being for use in packet switching-related operations in the network, the packet switching-related operations being programmable based upon configuration data to be received by the integrated circuit, the integrated circuit comprising:

an ingress pipeline to process packet data received by the integrated circuit via the ingress ports;

a shared queuing system to queue the packet data processed by the ingress pipeline; and

an egress pipeline to obtain, from the shared queuing system, the packet data processed by the ingress pipeline, and also to further process the packet data processed by the ingress pipeline;

wherein:

the ingress pipeline comprises a configurable parser and configurable match-action stages;

the egress pipeline comprises at least one other stage;

the configurable parser is to be configured, in accordance with the configuration data, to parse packet header fields to generate multiple sets of header field data;

the multiple sets of header field data comprise (1) at least one set of header field data for use by at least one of the match-action stages and (2) at least one other set of header field data;

the at least one of the match-action stages is to perform actions associated with at least certain portions of the at least one set of header field data;

the at least one of the match-action stages is to determine the actions based upon matching, at least in part, of the at least one set of header field data with match table data;

the match action table data is configurable to comprise both (1) ternary content addressable table data to be stored in the TCAM and (2) exact match table data;

the actions and the match action table data are to be configured based upon the configuration data;

the actions are configurable to comprise packet header data modification and/or packet data port assignment;

the at least one other stage is to generate output packet data for output from the integrated circuit;

the at least one other stage is to generate the output packet data based upon modified packet header data generated by the at least one of the match-action stages;

the output packet data is for output via at least one of the egress ports;

the at least one other set of header field data is unavailable for match-action stage modification; and

the parser is configurable, based upon the configuration data, to store the at least one set of header field data, at least in part, in containers of different sizes.

17. The hardware switch of claim 16 , wherein:

the parser is to extract the at least one set of header field data and the at least one other set of header field data in accordance with parse graph data that defines manner of header field extraction in terms of current bit field and next bit field for extraction; and

the parse graph data is to be defined by the configuration data.

18. The hardware switch of claim 17 , wherein:

the configuration data is to be generated by a compiler based upon user-written code; and

the compiler is not part of the integrated circuit.

19. The hardware switch of claim 18 , wherein:

the actions are also configurable to comprise:

address modification; and

packet data drop; and

the packet switching-related operations are configurable to comprise:

multi-layer tunneling protocol processing;

GENEVE/GRE protocol processing; and

variable field processing.

20. The hardware switch of claim 19 , wherein:

the configuration data is configurable to instruct the parser to determine when header end has been reached, and to stop parse graph traversal and header parsing.

Assignments (1)

Continuity (5)

References Cited (400)