Stacked FET with low parasitic-capacitance gate
A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.
1 . A semiconductor device comprising:
a top field effect transistor (FET);
a bottom FET, wherein the top FET and bottom FET are in a stacked profile;
a gate, wherein the gate comprises two top-FET gate sidewall extensions and two bottom-FET gate sidewall extensions, wherein the two top-FET gate sidewall extensions each comprise a gate bump;
an insulator liner that interfaces with the two top-FET gate sidewall extensions and two bottom-FET gate sidewall extensions; and
a dielectric that interfaces with the insulator liner.
2 . The semiconductor device of claim 1 , wherein the gate is self aligned within the dielectric.
3 . The semiconductor device of claim 1 , wherein the two top-FET gate sidewall extensions and two bottom-FET gate sidewall extensions are of a uniform thickness.
4 . The semiconductor device of claim 1 , wherein the gate further comprises a set of gate sheets, and wherein the gate sheets are of a uniform thickness.
5 . The semiconductor device of claim 4 , wherein the gate two top-FET gate sidewall extensions, the two bottom-FET gate sidewall extensions, and the gate sheets are of a uniform thickness.
6 . The semiconductor device of claim 1 , further comprising a set of sacrificial-channel spacers.
7 . The semiconductor device of claim 1 , further comprising a self-aligned-contact cap formed upon the gate.
8 . A semiconductor device comprising:
a top field effect transistor (FET), wherein the top FET comprises a first sidewall gate extension and a second sidewall gate extension, wherein the first sidewall gate extension and the second sidewall gate extension each comprise a gate bump; and
a bottom FET, wherein the bottom FET comprises a third sidewall gate extension and a fourth sidewall gate extension and wherein the top FET and bottom FET are in a stacked profile;
wherein the first, second, third, and fourth sidewall gate extensions are of equal thickness.
9 . The semiconductor device of claim 8 , wherein the top FET comprises a first set of gate sheets, the bottom FET comprises a second set of gate sheets, and wherein the gate sheets within the first and second set of gate sheets are of equal thickness to the first, second, third, and fourth sidewall gate extensions.
10 . The semiconductor device of claim 8 , wherein the top FET comprises a bottom gate sheet, wherein a portion of the bottom gate sheet comprises a middle dielectric isolation gate sheet, and wherein the middle dielectric isolation gate sheet is of equal thickness to the first, second, third, and fourth sidewall gate extensions.
11 . The semiconductor device of claim 8 , further comprising a middle dielectric isolation sheet, wherein the top FET comprises a first set of nanosheets that are of a width that is less than a width of the middle dielectric isolation sheet and wherein the bottom FET comprises a second set of nanosheets that are of a width that is equal to the middle dielectric isolation sheet.
12 . The semiconductor device of claim 8 , further comprising a set of sacrificial-channel spacers.
13 . The semiconductor device of claim 8 , further comprising:
an insulator liner that interfaces with the first, second, third, and fourth sidewall gate extensions; and
a dielectric that interfaces with the insulator liner.
14 . The semiconductor device of claim 8 , further comprising a self-aligned-contact cap.
15 . A semiconductor device comprising:
a top field effect transistor (FET), wherein the top FET comprises a first sidewall gate extension and a second sidewall gate extension;
a bottom FET, wherein the bottom FET comprises a third sidewall gate extension and a fourth sidewall gate extension and wherein the top FET and bottom FET are in a stacked profile;
an upper gate extension that connects to the first and second sidewall gate extension, wherein the upper gate extension extends over the bottom FET; and
a first dielectric fill located between the upper gate extension and the bottom FET;
wherein the first, second, third, and fourth sidewall gate extensions are of equal thickness.
16 . The semiconductor device of claim 15 , wherein the top FET comprises a first set of gate sheets, the bottom FET comprises a second set of gate sheets, and wherein the gate sheets within the first and second set of gate sheets are of equal thickness to the first, second, third, and fourth sidewall gate extensions.
17 . The semiconductor device of claim 15 , further comprising:
a first dielectric fill that interfaces with the first and third sidewall gate extensions;
a second dielectric fill that interfaces with the second and fourth sidewall gate extensions;
a first gate cut through the upper gate extension, wherein the first gate cut interfaces with the first dielectric fill; and
a second gate cut through the upper gate extension, wherein the second gate cut interfaces with the second dielectric fill.