IP Library › Patent Application 18221976
Patent Application
App. No. 18/221,976

Method for Forming Mixed Substrate

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Patent No.
US None
App. No.
18/221,976
Abstract

The present application discloses a method for forming a mixed substrate. By optimizing the process flow, adding a silicon oxide sidewall process and covering an SOI area sidewall after dry etching with protective silicon oxide, epitaxial silicon growth on the SOI area sidewall is prevented, so that a bulge is prevented from being formed at a boundary between an SOI area and a silicon substrate area when the silicon substrate area is formed on an SOI silicon wafer. At the same time, since STI is eventually formed at the boundary between the SOI area and the silicon substrate area, the actual structure of a device formed on the mixed substrate remains basically unchanged, thus improving the product yield. The method for forming the mixed substrate is particularly suitable for an SOI gate-last process.

Claims (17)

1 . A method for forming a mixed substrate, comprising the following steps:

S1: depositing a layer of mask silicon oxide on a silicon-on-insulator (SOI) silicon wafer, and then depositing a layer of mask silicon nitride;

S2: performing a photolithography process to open a silicon substrate area in which a silicon substrate is to be formed;

S3: performing dry etching to remove the mask silicon nitride, the mask silicon oxide, SOI, and buried silicon oxide (BOX) above substrate silicon in the silicon substrate area;

S4: removing photoresist;

S5: oxidizing silicon on an upper surface of the substrate silicon in the silicon substrate area and a side surface of an SOI area to form protective silicon oxide;

S6: depositing supplementary silicon oxide;

S7: performing dry etching to remove silicon oxide on the substrate silicon in the silicon substrate area; and

S8: performing epitaxial silicon growth to enable the upper surface of the substrate silicon in the silicon substrate area to grow flush with an upper surface of SOI in the SOI area.

2 . The method for forming the mixed substrate according to claim 1 , wherein shallow trench isolation (STI) is formed at a boundary between the SOI area and the silicon substrate area.

3 . The method for forming the mixed substrate according to claim 1 , wherein the supplementary silicon oxide is atomic layer deposition (ALD) silicon oxide.

4 . The method for forming the mixed substrate according to claim 1 , wherein a thickness of the supplementary silicon oxide is 4-20 nm.

5 . The method for forming the mixed substrate according to claim 1 , wherein in step S1, a thickness of the mask silicon oxide is 3-10 nm, and a thickness of the mask silicon nitride is 10-30 nm.

6 . The method for forming the mixed substrate according to claim 1 , wherein, after dry etching in step S7, wet cleaning is performed and then step S8 is performed.

7 . The method for forming the mixed substrate according to claim 1 , wherein, in step S5, the silicon on the upper surface of the substrate silicon in the silicon substrate area and the side surface of the SOI in the SOI area is oxidized to form the protective silicon oxide through a rapid thermal oxidation (RTO) process.

8 . The method for forming the mixed substrate according to claim 1 , wherein, in step S5, a thickness of the protective silicon oxide formed by oxidizing the silicon on the upper surface of the substrate silicon in the silicon substrate area and the side surface of the SOI in the SOI area is 6-12 nm.

9 . The method for forming the mixed substrate according to claim 1 , wherein, in step S7, dry etching is performed to remove silicon oxide in the silicon substrate area, and a lateral thickness of remaining silicon oxide on the side surface of the SOI in the SOI area is enabled to be greater than 3 nm.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: SHANGHAI HUALI MICROELECTRONICS CORPORATION
To: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
Reel/Frame 072141/0132 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2023
From: WANG, TAO
To: SHANGHAI HUALI MICROELECTRONICS CORPORATION
Reel/Frame 064259/0400 →