Granted Patent B2

US 12,656,798 · App. 18/224,897 · Granted Jun 16, 2026

Inventors: Umberto Ferlito (Catania, IT); Michele Vaiana (San Giovanni la Punta, IT); Giuseppe Bruno (Paterno', IT); Alfio Dario Grasso (Riposto, IT)

Assignee: STMicroelectronics S.r.l.

G05F1/565G05F1/575G05F3/262

Abstract

Claims (88)

1 . A circuit, comprising:

a voltage regulator circuit configured to generate a regulated voltage at an output node;

a transistor coupled between the output node and a reference node; and

a mode selection circuit coupled to a control terminal of the transistor and including a first current source and a second current source, the mode selection circuit configured to: control the transistor to sink a current mirrored from a current output of the first current source from said output node to the reference node in response to a first logic state of a mode control signal, and sink a current mirrored from a current output of the second current source from the control terminal of the transistor in response to a second logic state of the mode control signal in order to turn off said transistor at a controlled rate.

2 . A circuit, comprising:

a voltage regulator circuit configured to generate a regulated voltage at an output node;

a transistor coupled between the output node and a reference node; and

a mode selection circuit coupled to a control terminal of the transistor and configured to: control the transistor to sink a current with a controlled magnitude from said output node to the reference node in response to a first logic state of a mode control signal, and sink a current with a controlled magnitude from the control terminal of the transistor in response to a second logic state of the mode control signal in order to turn off said transistor at a controlled rate;

wherein said mode selection circuit comprises:

a first current conduction path including a first current source configured to source a first current, said first current conduction path enabled in response to the first logic state of the mode control signal;

wherein said first current conduction path is coupled in a first current mirroring relationship with the transistor.

3 . The circuit of claim 2 , wherein said mode selection circuit further comprises:

a second current conduction path including a second current source configured to source a second current, said second current conduction path enabled in response to the second logic state of the mode control signal;

wherein said second current conduction path is coupled in a second current mirroring relationship with a sinking transistor; and

wherein said sinking transistor is coupled to the control terminal of the transistor.

4 . The circuit of claim 2 , wherein the first current mirroring relationship includes coupling transistors connected in series with the control terminal of the transistor, said coupling transistors having control terminals configured to be switched to a conductive state in response to the first logic state of the mode control signal.

5 . The circuit of claim 2 , further comprising a control circuit configured to generate said mode control signal.

6 . The circuit of claim 5 , wherein said control circuit asserts the mode control signal in the first logic state in response to a transition of the voltage regulator circuit from a low-power mode to a high-power mode with respect to a load coupled to the output node.

7 . The circuit of claim 6 , wherein said control circuit deasserts the mode control signal in the second logic state in response to a transition of the voltage regulator circuit from the high-power mode to the low-power mode with respect to the load coupled to the output node.

8 . A method, comprising:

producing a regulated output voltage at an output node; and

selectively controlling a transistor coupled between the output node and a reference node;

wherein selectively controlling comprises:

controlling the transistor to sink a current mirrored from a current output of a first current source from said output node to the reference node in response to a first logic state of a mode control signal; and

sinking a current mirrored from a current output of a second current source from a control terminal of the transistor in response to a second logic state of the mode control signal in order to turn off said transistor at a controlled rate.

9 . A circuit, comprising:

a first input terminal and a second input terminal configured to receive an input voltage therebetween;

a first output terminal and a second output terminal configured to produce a regulated output voltage therebetween, wherein the second input terminal and the second output terminal are coupled to a ground node;

a feedback network configured to produce a feedback voltage indicative of the regulated output voltage;

an error amplifier configured to produce a drive signal as a function of a difference between said feedback voltage and a reference voltage;

a pass element arranged between said first input terminal and said first output terminal, wherein a conductivity of said pass element is modulated as a function of said drive signal;

an output transistor arranged between said first output node and said ground node; and

a mode selection circuit configured to receive a mode selection signal and control said output transistor as a function thereof, wherein:

in response to assertion of said mode selection signal, said mode selection circuit controls turn on said output transistor to sink a current mirrored from a current output of a first current source from said first output node; and

in response to de-assertion of said mode selection signal, said mode selection circuit sinks a current mirrored from a current output of a second first current source from a control terminal of said output transistor to control turn off said output transistor at a controlled rate.

10 . The circuit of claim 9 , wherein said mode selection signal is asserted in response to a transition from a low-power mode to a high-power mode with respect to a load coupled between the first output terminal and the second output terminal.

11 . The circuit of claim 10 , wherein said mode selection signal is de-asserted in response to a transition from the high-power mode to the low-power mode with respect to the load coupled between the first output terminal and the second output terminal.

12 . A circuit, comprising:

a first input terminal and a second input terminal configured to receive an input voltage therebetween;

a first output terminal and a second output terminal configured to produce a regulated output voltage therebetween, wherein the second input terminal and the second output terminal are coupled to a ground node;

a feedback network configured to produce a feedback voltage indicative of the regulated output voltage;

an error amplifier configured to produce a drive signal as a function of a difference between said feedback voltage and a reference voltage;

a pass element arranged between said first input terminal and said first output terminal, wherein a conductivity of said pass element is modulated as a function of said drive signal;

an output transistor arranged between said first output node and said ground node; and

a mode selection circuit configured to receive a mode selection signal and control said output transistor as a function thereof, wherein:

in response to assertion of said mode selection signal, said mode selection circuit controls turn on said output transistor to sink a current with a controlled magnitude from said first output node; and

in response to de-assertion of said mode selection signal, said mode selection circuit sinks a current with a controlled magnitude from a control terminal of said output transistor to turn off said output transistor at a controlled rate;

wherein said mode selection circuit comprises a first current conduction path including a first current source configured to source a first current, an enabling transistor, and a diode-connected transistor arranged in series between a power supply node and said ground node,

wherein said enabling transistor is switched to a conductive state in response to assertion of said mode selection signal and switched to a non-conductive state in response to de-assertion of said mode selection signal, and

wherein said diode-connected transistor and said output transistor are coupled to form a current mirror.

13 . The circuit of claim 12 , wherein said mode selection circuit comprises one or more coupling transistors with current conduction paths arranged in series between a control terminal of said diode-connected transistor and a control terminal of said output transistor, wherein said one or more coupling transistors are switched to a conductive state in response to assertion of said mode selection signal and switched to a non-conductive state in response to de-assertion of said mode selection signal.

14 . The circuit of claim 12 , wherein said mode selection circuit further comprises a capacitor coupled between a control terminal of said enabling transistor and said ground node.

15 . The circuit of claim 12 , wherein said mode selection circuit further comprises a gate-controlling transistor having a current conduction path arranged between a control terminal of said diode-connected transistor and said ground node, wherein said gate-controlling transistor is controlled in response to a complement of said mode selection signal, wherein the gate-controlling transistor is switched to a conductive state in response to de-assertion of said mode selection signal and switched to a non-conductive state in response to assertion of said mode selection signal.

16 . A circuit, comprising:

a first input terminal and a second input terminal configured to receive an input voltage therebetween;

a first output terminal and a second output terminal configured to produce a regulated output voltage therebetween, wherein the second input terminal and the second output terminal are coupled to a ground node;

a feedback network configured to produce a feedback voltage indicative of the regulated output voltage;

an error amplifier configured to produce a drive signal as a function of a difference between said feedback voltage and a reference voltage;

a pass element arranged between said first input terminal and said first output terminal, wherein a conductivity of said pass element is modulated as a function of said drive signal;

an output transistor arranged between said first output node and said ground node; and

a mode selection circuit configured to receive a mode selection signal and control said output transistor as a function thereof, wherein:

in response to assertion of said mode selection signal, said mode selection circuit controls turn on said output transistor to sink a current with a controlled magnitude from said first output node; and

in response to de-assertion of said mode selection signal, said mode selection circuit sinks a current with a controlled magnitude from a control terminal of said output transistor to turn off said output transistor at a controlled rate;

wherein said mode selection circuit comprises a current mirror arrangement configured to selectively sink a second current from said control terminal of said output transistor in response to de-assertion of said mode selection signal.

17 . The circuit of claim 16 , wherein said mode selection circuit comprises a further enabling transistor having a current conduction path arranged between said current mirror arrangement and said control terminal of said output transistor, wherein said further enabling transistor is configured to receive a complement of said mode selection signal, wherein the further enabling transistor is switched to a conductive state in response to de-assertion of said mode selection signal and switched to a non-conductive state in response to assertion of said mode selection signal.

18 . The circuit of claim 16 , wherein said mode selection circuit comprises a further gate-controlling transistor having a current conduction path arranged between a control terminal of said current mirror arrangement and said ground node, wherein said further gate-controlling transistor is configured to receive said mode selection signal, wherein the further gate-controlling transistor is switched to a conductive state in response to assertion of said mode selection signal and switched to a non-conductive state in response to de-assertion of said mode selection signal.

19 . A circuit, comprising:

a first input terminal and a second input terminal configured to receive an input voltage therebetween;

a first output terminal and a second output terminal configured to produce a regulated output voltage therebetween, wherein the second input terminal and the second output terminal are coupled to a ground node;

a feedback network configured to produce a feedback voltage indicative of the regulated output voltage;

an error amplifier configured to produce a drive signal as a function of a difference between said feedback voltage and a reference voltage;

a pass element arranged between said first input terminal and said first output terminal, wherein a conductivity of said pass element is modulated as a function of said drive signal;

an output transistor arranged between said first output node and said ground node; and

a mode selection circuit configured to receive a mode selection signal and control said output transistor as a function thereof, wherein:

in response to assertion of said mode selection signal, said mode selection circuit controls turn on said output transistor to sink a current with a controlled magnitude from said first output node; and

in response to de-assertion of said mode selection signal, said mode selection circuit sinks a current with a controlled magnitude from a control terminal of said output transistor to turn off said output transistor at a controlled rate;

a capacitor coupled between the control terminal of said output transistor and a control terminal of said pass element; and

an output capacitor coupled between said first output node and said second output node.

20 . A method of operating a voltage regulator circuit, comprising:

receiving an input voltage between a first input terminal and a second input terminal;

producing a regulated output voltage between a first output terminal and a second output terminal;

producing a feedback voltage indicative of the regulated output voltage at a feedback network;

producing a drive signal as a function of a difference between said feedback voltage and a reference voltage at an error amplifier;

applying said drive signal to control modulation of a conductivity of a pass element as a function of said drive signal;

receiving a mode selection signal and controlling an output transistor as a function of said mode selection signal;

wherein controlling comprises:

in response to assertion of said mode selection signal, turning on said output transistor to sink a current mirrored from a current output of a first current source from said first output terminal; and

in response to de-assertion of said mode selection signal, sinking a current mirrored from a current output of a second current source from a control terminal of said output transistor to turn off said output transistor at a controlled rate.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (17)