Semiconductor structure and method for manufacturing the same
View Patent ↗A semiconductor structure includes a first dielectric layer, a first metal feature in the first dielectric layer, at least one etch stop layer on the first dielectric layer, a second dielectric layer on the at least one etch stop layer. The semiconductor structure further includes a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer, a second barrier sublayer on the first barrier sublayer and the first metal feature, and a second metal feature on the second barrier sublayer.
1. A semiconductor structure, comprising:
a first dielectric layer;
a first metal feature in the first dielectric layer;
at least one etch stop layer on the first dielectric layer;
a second dielectric layer on the at least one etch stop layer;
a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer;
a second barrier sublayer on the first barrier sublayer and the first metal feature; and
a second metal feature on the second barrier sublayer.
2. The semiconductor structure of claim 1 , wherein the first barrier sublayer comprises a metal nitride, and the second barrier sublayer comprises a transition metal.
3. The semiconductor structure of claim 2 , further comprising a cap layer on a top surface of the second metal feature.
4. The semiconductor structure of claim 1 , wherein the at least one etch stop layer comprises a first etch stop layer, a second etch stop layer and a third etch stop layer.
5. The semiconductor structure of claim 4 , wherein the first etch stop layer comprises a first material, the second etch stop layer comprises a second material, and the third etch stop layer comprises a third material, wherein the second material is different from the first and third materials.
6. The semiconductor structure of claim 5 , wherein the first etch stop layer comprises aluminum nitride, the second etch stop layer comprises aluminum oxide, and the third etch stop layer comprises aluminum nitride.
7. A semiconductor structure, comprising:
a first dielectric layer;
a first metal feature in the first dielectric layer;
at least one etch stop layer on the first dielectric layer;
a second dielectric layer on the at least one etch stop layer, wherein the second dielectric layer comprises an implanted region along a sidewall of the second dielectric layer;
a barrier layer comprising:
a first barrier sublayer on the sidewall of the second dielectric layer and the at least one etch stop layer; and
a second barrier sublayer on the first barrier sublayer and the first metal feature; and
a second metal feature on the barrier layer.
8. The semiconductor structure of claim 7 , wherein the implanted region comprises:
a first implanted region along the sidewall of the second dielectric layer; and
a second implanted region adjacent the first implanted region, wherein the first implanted region is between the sidewall of the second dielectric layer and the second implanted region, and a dopant concentration of the first implanted region is greater than a dopant concentration of the second implanted region.
9. The semiconductor structure of claim 8 , wherein the dopant comprises germanium or argon.
10. The semiconductor structure of claim 7 , wherein the
first barrier sublayer in contact with the first metal feature.
11. The semiconductor structure of claim 7 , wherein the
second barrier sublayer is in contact with at least a portion of a top of the first metal feature.
12. The semiconductor structure of claim 7 , wherein the at least one etch stop layer comprises a first etch stop layer, a second etch stop layer and a third etch stop layer.
13. The semiconductor structure of claim 12 , wherein the first etch stop layer comprises aluminum nitride, the second etch stop layer comprises aluminum oxide, and the third etch stop layer comprises aluminum nitride.
14. A semiconductor structure, comprising:
a first dielectric layer;
a first metal feature in the first dielectric layer;
a first etch stop layer on the first dielectric layer;
a second etch stop layer on the first etch stop layer;
a third etch stop layer on the second etch stop layer;
a second dielectric layer on the third etch stop layer;
a first barrier sublayer on a sidewall of the second dielectric layer and the first, second, and third etch stop layers;
a second barrier sublayer on the first barrier sublayer and the first metal feature; and
a second metal feature on the second barrier sublayer.
15. The semiconductor structure of claim 14 , wherein the second etch stop layer is formed from a material different than materials in the first and second etch stop layer.
16. The semiconductor structure of claim 14 , wherein the second barrier sublayer is in contact with the first metal feature.
17. The semiconductor structure of claim 14 , wherein the first barrier sublayer is in contact with the first metal feature.
18. The semiconductor structure of claim 17 , wherein the second dielectric layer includes a first implanted region and a second implanted region, the first implanted region is along the sidewall of the second dielectric layer and the second implanted region is adjacent the first implanted region, wherein the first implanted region is between the sidewall of the second dielectric layer and the second implanted region.
19. The semiconductor structure of claim 18 , wherein a dopant concentration of the first implanted region is greater than a dopant concentration of the second implanted region.
20. The semiconductor structure of claim 18 , wherein the dopant comprises one of germanium and argon.