IP Library › Granted Patent US 12,635,224
Granted Patent B2
US 12,635,224 · App. 18/230,020 · Granted May 19, 2026

Method of manufacturing semiconductor devices and semiconductor devices

Inventors: Chandrashekhar Prakash Savant (Hsinchu, TW); Chia-Ming Tsai (Zhubei, TW); Ming-Te Chen (Hsinchu, TW); Tien-Wei Yu (Kaohsiung, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D84/038H10D84/0167H10D84/0177H10D84/85
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Quick Facts
Patent No.
US 12,635,224
App. No.
18/230,020
Granted
May 19, 2026
Kind
B2
Abstract

A semiconductor device includes a gate structure disposed over a channel region, and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, a first work function adjustment layer, over the gate dielectric layer, a first shield layer over the first work function adjustment layer, a first barrier layer, and a metal gate electrode layer. The first work function adjustment layer is made up of n-type work function adjustment layer and includes aluminum. The first shield layer is made of at least one selected from the group consisting of metal, metal nitride, metal carbide, silicide, a layer containing one or more of F, Ga, In, Zr, Mn and Sn, and an aluminum containing layer having a lower aluminum concentration than the first work function adjustment layer.

Claims (39)

1 . A method of manufacturing a semiconductor device, comprising:

forming a gate dielectric layer over a channel region made of a semiconductor material;

forming a first shield layer over the gate dielectric layer;

forming a first work function adjustment layer over the first shield layer;

forming a second shield layer over the first work function adjustment layer;

forming a metal gate electrode layer over the first shield layer, wherein:

the second shield layer is a surface region of the first work function adjustment layer,

the first work function adjustment layer includes aluminum, and

at least one of the first shield layer or the second shield layer includes one selected from the group consisting of a metal layer, a metal nitride layer comprising TaTiN, WN, WCN or MoN, a metal carbide layer, a silicide layer, and a layer containing Al and one or more of F, N, Ga, In, Zr, Mn and Sn.

2 . The method of claim 1 , wherein the second shield layer contains Al and F.

3 . The method of claim 2 , wherein the second shield layer is formed by treating a surface of the first work function adjustment layer with fluorine containing material.

4 . The method of claim 3 , wherein the fluorine containing material includes HF.

5 . The method of claim 1 , wherein the second shield layer contains Al and N.

6 . The method of claim 5 , wherein the second shield layer is formed by treating a surface of the first work function adjustment layer with a NH 3 gas.

7 . The method of claim 1 , wherein the second shield layer contains one or more of Ga, In, Zr, Mn and Sn.

8 . The method of claim 1 , wherein the second shield layer is formed by implanting ions of one or more of Ga, In, Zr, Mn and Sn to the surface region of the first work function adjustment layer.

9 . A method of manufacturing a semiconductor device, comprising:

forming a gate dielectric layer over a channel region made of a semiconductor material;

forming a first shield layer over the gate dielectric layer;

forming a first work function adjustment layer over the first shield layer;

forming a second shield layer by introducing one or more elements into a surface region of the first work function adjustment layer;

forming a metal gate electrode layer over the first shield layer.

10 . The method of claim 9 , wherein the first work function adjustment layer includes aluminum.

11 . The method of claim 10 , wherein the first shield layer includes a metal layer.

12 . The method of claim 10 , wherein the first shield layer includes a metal nitride layer comprising TaTiN, WN, WCN or MoN.

13 . The method of claim 10 , wherein the first shield layer includes a metal carbide layer.

14 . The method of claim 10 , wherein the first shield layer includes a silicide layer.

15 . The method of claim 10 , wherein the second shield layer includes a layer containing Al and F.

16 . The method of claim 10 , wherein the second shield layer includes a layer containing Al and N.

17 . The method of claim 10 , wherein the second shield layer includes a layer containing Al and one or more of Ga, In, Zr, Mn or Sn.

18 . A method of manufacturing a semiconductor device, comprising:

forming a gate dielectric layer over a channel region made of a semiconductor material;

forming a first shield layer over the gate dielectric layer;

forming a first work function adjustment layer over the first shield layer;

forming a second shield layer by introducing one or more elements into a surface region of the first work function adjustment layer;

forming a metal gate electrode layer over the first shield layer,

wherein the second shield layer includes a layer containing Al and one or more of F, N, Ga, In, Zr, Mn and Sn.

19 . The method of claim 18 , wherein the first shield layer includes one selected from the group consisting of a metal layer, a metal nitride layer comprising TaTiN, WN, WCN or MoN, a metal carbide layer, and a silicide layer.

20 . The method of claim 18 , wherein the one or more elements are introduced by ion implantation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2023
From: SAVANT, CHANDRASHEKHAR PRAKASH; TSAI, CHIA-MING; CHEN, MING-TE; YU, TIEN-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 065349/0602 →
Continuity (3)
Division 17532852 · Nov 22, 2021
Continuation 16562395 · Sep 5, 2019
Related Publication 20230377994A1 · Nov 23, 2023
References Cited (26)
US 9064732B2 · Yu et al. · 2015 [cited by applicant]
US 9202698B2 · Jagannathan et al. · 2015 [cited by applicant]
US 9502416B1 · Kim · 2016 [cited by applicant]
US 10157998B2 · Wang et al. · 2018 [cited by applicant]
US 10211309B2 · Zhou · 2019 [cited by applicant]
US 10937783B2 · Chang et al. · 2021 [cited by applicant]
US 20100081262A1 · Lim et al. · 2010 [cited by applicant]
US 20140070307A1 · Ando et al. · 2014 [cited by applicant]
US 20150021699A1 · Ando et al. · 2015 [cited by applicant]
US 20150194423A1 · Wang et al. · 2015 [cited by applicant]
US 20160380066A1 · Lin et al. · 2016 [cited by applicant]
US 20170110553A1 · Zhou · 2017 [cited by applicant]
US 20180323300A1 · Wang et al. · 2018 [cited by applicant]
US 20190067117A1 · Chen et al. · 2019 [cited by applicant]
US 20190103390A1 · Chen et al. · 2019 [cited by applicant]
CN 106158932A · 2016 [cited by applicant]
CN 106601605A · 2017 [cited by applicant]
CN 106847874A · 2017 [cited by applicant]
CN 107887428A · 2018 [cited by applicant]
CN 108122909A · 2018 [cited by applicant]
CN 108257918A · 2018 [cited by applicant]
KR 1020170002261A · 2017 [cited by applicant]
KR 1020190022280A · 2019 [cited by applicant]
Chris Auth et al., “45nm High-k+Metal Gate Strain-Enhanced Transistors,” Intel Technology Journal, vol. 12, Issue 02, pp. 77-85, Published Jun. 17, 2008, ISSN 1535-864X, DOI: 10.1535/itj.1202. [cited by applicant]
Non-Final Office Action issued in U.S. Appl. No. 16/562,395, dated Apr. 1, 2021. [cited by applicant]
Notice of Allowance issued in U.S. Appl. No. 16/562,395, dated Jul. 16, 2021. [cited by applicant]