Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
1. A semiconductor device, comprising:
first and second semiconductor wires vertically arranged and alternately stacked, and each having a channel region;
a source/drain epitaxial layer connected to the first and the second semiconductor wires;
a gate structure formed around the first and the second semiconductor wires;
a dielectric inner spacer disposed between the gate structure and the source/drain epitaxial layer; and
a gate sidewall spacer made of a different material than a material of the dielectric inner spacer,
wherein a cross section of the second semiconductor wires has a dog-bone shape or a thread-spool shape.
2. The semiconductor device of claim 1 , wherein the first semiconductor wires are made of Si 1-x Ge x , where 0.45≤x.
3. The semiconductor device of claim 2 , wherein the second semiconductor wires are made of Si or S 1-y Ge y , where 0<y≤0.2.
4. The semiconductor device of claim 1 , wherein a width of the first and the second semiconductor wires is smaller than a thickness thereof.
5. The semiconductor device of claim 1 , wherein a thickness of the first and the second semiconductor wires is greater than a space between adjacent semiconductor wires.
6. The semiconductor device of claim 1 , wherein the semiconductor device is a p-channel field effect transistor.
7. The semiconductor device of claim 1 , wherein the source/drain epitaxial layer wraps around source/drain regions of the semiconductor wires.
8. The semiconductor device of claim 1 , wherein the material of the gate sidewall spacer is SiOC, SiCON, or SiCN.
9. The semiconductor device of claim 8 , wherein the material of the dielectric inner spacer is silicon nitride.
10. A semiconductor device comprising:
an n-channel field effect transistor (FET) comprising:
first semiconductor wires vertically arranged each having a first channel region;
a first source/drain epitaxial layer connected to the first semiconductor wires;
a first gate structure formed around the first semiconductor wires;
a first dielectric inner spacer disposed between the first gate structure and the first source/drain epitaxial layer; and
a first gate sidewall spacer made of a different material than a material of the first dielectric inner spacer; and
a p-channel FET comprising:
second semiconductor wires vertically arranged each having a second channel region;
a second source/drain epitaxial layer connected to the second semiconductor wires;
a second gate structure formed around the second semiconductor wires;
a second dielectric inner spacer disposed between the second gate structure and the second source/drain epitaxial layer; and
a second gate sidewall spacer made of a different material than a material of the second dielectric inner spacer,
wherein a cross section of the second semiconductor wires has a dog-bone shape or a thread-spool shape.
11. The semiconductor device of claim 10 , wherein the second semiconductor wires are made of Si 1-x Ge x , where 0.45≤x, and wherein the first semiconductor wires are made of Si or Si 1-y Ge y , where 0<y≤0.2.
12. The semiconductor device of claim 10 , wherein the second semiconductor wires are made of Si 1-x Ge x , where 0.45≤x≤0.55, and wherein the first semiconductor wires are made of Si.
13. The semiconductor device of claim 10 , wherein a width of the second semiconductor wires is smaller than a width of the first semiconductor wires.
14. The semiconductor device of claim 10 , wherein a width of the second semiconductor wires is smaller than a thickness of the first semiconductor wires and a thickness of the second semiconductor wires.
15. The semiconductor device of claim 10 , wherein the first source/drain epitaxial layer wraps around source/drain regions of the first semiconductor wires.
16. The semiconductor device of claim 10 , wherein the second source/drain epitaxial layer wraps around source/drain regions of the second semiconductor wires.
17. The semiconductor device of claim 10 , wherein the first source/drain epitaxial layer is formed on end faces of the first semiconductor wires.
18. A semiconductor device, comprising:
a first p-channel field effect transistor (FET) comprising:
first semiconductor wires vertically arranged each having a channel region;
a first source/drain epitaxial layer connected to the first semiconductor wires;
a first gate structure formed around the first semiconductor wires; and
a first dielectric inner spacer disposed between the first gate structure and the first source/drain epitaxial layer; and
a first gate sidewall spacer made of a different material than a material of the first dielectric inner spacer; and
a second p-channel FET comprising:
second and third semiconductor wires alternately stacked each having a channel region;
a second source/drain epitaxial layer connected to the second and the third semiconductor wires;
a second gate structure formed around the second and the third semiconductor wires;
a second dielectric inner spacer disposed between the second gate structure and the second source/drain epitaxial layer; and
a second gate sidewall spacer made of a different material than a material of the second dielectric inner spacer,
wherein a cross section of the third semiconductor wires has a dog-bone shape or a thread-spool shape.
19. The semiconductor device of claim 18 , wherein the first semiconductor wires are made of Si 1-x Ge x , where 0.45≤x, and wherein the second semiconductor wires are made of Si or Si 1-y Ge y , where 0<y≤0.2.
20. The semiconductor device of claim 18 , wherein the first and the second dielectric inner spacers are made of silicon nitride.