Channel structures for semiconductor devices
View Patent ↗The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.
1. A semiconductor device, comprising:
a substrate;
a base structure disposed on the substrate;
first and second spacers disposed on the base structure;
a channel structure, disposed on the base structure, comprising:
a nanostructured channel region disposed between the first and second pairs of spacers, and
a cladding layer surrounding portions of the nanostructured channel region that are uncovered by the first and second pairs of spacers, wherein the cladding layer comprises a germanium layer;
a gate structure surrounding the channel structure; and
a source/drain (S/D) region disposed adjacent to the nanostructured channel region.
2. The semiconductor device of claim 1 , wherein the cladding layer comprises a silicon germanium layer.
3. The semiconductor device of claim 1 , wherein the cladding layer comprises a concentration of germanium atoms between about 10% and about 40%.
4. The semiconductor device of claim 1 , wherein an outer surface of the cladding layer is substantially uniform with an outer surface of the nanostructured channel region.
5. The semiconductor device of claim 1 , wherein the cladding layer comprises a thickness less than about 2 nm.
6. The semiconductor device of claim 1 , wherein the cladding layer comprises an elliptical cross-sectional profile.
7. The semiconductor device of claim 1 , wherein the gate structure comprises a high-k dielectric layer; and
wherein the high-k dielectric layer is disposed on and in contact with the cladding layer.
8. The semiconductor device of claim 1 , further comprising another cladding layer disposed on a top surface of the base structure.
9. The semiconductor device of claim 8 , wherein the other cladding layer comprises a germanium layer or a silicon germanium layer.
10. The semiconductor device of claim 1 , wherein the nanostructured channel region comprises a single semiconductor layer extending from a sidewall of the cladding layer to inner surfaces of the cladding layer.
11. A semiconductor device, comprising:
a substrate;
a fin-shaped base structure disposed on the substrate;
first and second nanostructured channel regions disposed on the fin-shaped base structure;
first and second cladding layers surrounding the first and second nanostructured channel regions, respectively;
a third cladding layer disposed on a top surface and sidewalls of the fin-shaped base structure, wherein the third cladding layer comprises end portions with tapered cross-sectional profiles disposed on the sidewalls of the fin-shaped base structure;
a gate structure surrounding the first and second cladding layers; and
a source/drain (S/D) region disposed adjacent to the first and second nanostructured channel regions, wherein the first cladding layer is separated from the S/D region by a portion of the first nanostructured channel region.
12. The semiconductor device of claim 11 , wherein the first nanostructured channel region is disposed on the second nanostructured channel region.
13. The semiconductor device of claim 11 , wherein each of the first and second cladding layers comprises a germanium layer or a silicon germanium layer.
14. The semiconductor device of claim 11 , wherein each of the first and second cladding layers comprises a concentration of germanium atoms of about 20% to about 30%.
15. The semiconductor device of claim 11 , wherein the first and second cladding layers are separated from each other by a vertical distance of about 5 nm to about 10 nm.
16. The semiconductor device of claim 11 , wherein the gate structure comprises a dielectric layer; and
wherein the dielectric layer is disposed on and in contact with the first and second cladding layers.
17. A semiconductor device, comprising:
a substrate;
a silicon nanostructured channel region disposed on the substrate;
a germanium cladding layer surrounding the silicon nanostructured channel region;
a gate structure surrounding the germanium cladding layer; and
a source/drain (S/D) region disposed adjacent to the gate structure.
18. The semiconductor device of claim 17 , wherein the germanium cladding layer comprises a concentration of germanium atoms between about 10% and about 40%.
19. The semiconductor device of claim 17 , wherein the gate structure comprises a high-k dielectric layer; and
wherein the high-k dielectric layer is disposed on and in contact with the germanium cladding layer.
20. The semiconductor device of claim 17 , wherein the germanium cladding layer comprises a thickness less than about 2 nm.