Permuting in a matrix-vector processor
A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.
1. A special-purpose hardware integrated circuit, the circuit comprising:
a memory configured to store an input matrix and an output matrix;
a permute unit coupled to the memory, wherein the permute unit comprises:
an input register that stores input vectors corresponding to the input matrix;
a control register configured to store a control vector of control signals;
a permute execution circuit coupled to the input register and the control register, the permute execution circuit being configured to:
i) compute a matrix permutation of the input matrix by permuting the input vectors based on the control signals of the control vector; and
ii) generate the output matrix as a permutation of the input matrix.
2. The circuit of claim 1 , wherein the permute execution circuit computes the matrix permutation of the input matrix by multiplying, in hardware, the input matrix with a permutation matrix.
3. The circuit of claim 2 , wherein:
i) the permutation matrix is an identity matrix comprising an n×n matrix that has a plurality of ones, “1s”, along a principal diagonal of the identity matrix; and
ii) the principal diagonal extends from a (0,0) position to the (n,n) position of the identity matrix.
4. The circuit of claim 1 , wherein the permute unit is configured to perform an entire permutation of the input matrix based on a set of received information and without additional instructions from a source external to the permute unit.
5. The circuit of claim 4 , wherein the set of received information comprises control signals, a matrix input, a vector input, and permutation parameters.
6. The circuit of claim 5 , wherein the permutation parameters comprise a permutation matrix comprising data that indicates whether the matrix permutation is a row permutation or a column permutation.
7. The circuit of claim 5 , wherein the control vector of control signals is generated based on the permutation parameters.
8. The circuit of claim 7 , wherein the control vector of control signals comprises elements that specify a number of positions to rotate corresponding elements of the input vectors that correspond to the input matrix.
9. The circuit of claim 7 , wherein the control vector of control signals comprises elements that represent pointers to where elements of the input vectors corresponding to the input matrix are to be stored in a memory of the special-purpose hardware integrated circuit.
10. The circuit of claim 7 , wherein:
i) the control signals of the control vector are represented by data stored in the control register; and
ii) the data representing the control signals is used for controlling the permute execution circuit to perform a permutation of the input vectors stored in the input register.
11. The circuit of claim 7 , wherein the control vector of control signals comprises elements that indicate positions where corresponding elements of the input vectors are to be included and stored in an output vector of the output matrix.
12. The circuit of claim 7 , wherein the permute execution circuit comprises:
a plurality of multiplexors that are coupled to the input register, each of the plurality of multiplexors being configured to:
i) receive elements of an input vector stored in the input register; and
ii) generate an output vector that is a permutation of the input vector stored in the input register.
13. The circuit of claim 12 , the plurality of multiplexors corresponds to a number of elements of the input register.
14. The circuit of claim 12 , wherein:
i) each of the plurality of multiplexors is configured as an n-to-one multiplexor; and
ii) n corresponds to a dimension of the input matrix that the permute unit is configured to process.
15. The circuit of claim 14 , wherein the control signals of the control vector stored at the control register are used in controlling outputs of the plurality of multiplexors of the permute execution circuit.