MEMS device built using the BEOL metal layers of a solid state semiconductor process
A MEMS device formed using the materials of the BEOL of a CMOS process where a post-processing of vHF and post backing was applied to form the MEMS device and where a total size of the MEMS device is between 50 um and 150 um. The MEMS device may be implemented as an inertial sensor among other applications.
1. An integrated circuit chip comprising:
a first region filled with metal filling structures implementing a substantially constant metal density;
a second region not filled with the metal filling structures including:
a MEMS device formed using the materials of the BEOL of a CMOS process, wherein
a post-processing of vHF and post backing was applied to form the MEMS device after the first region is filled with the metal filling structures; and
wherein the MEMS device includes a pad, pad including a top metal layer arranged to extend laterally beyond a vertically aligned passivation opening in all directions preventing etching of dielectric material beyond the top metal layer during the post-processing of vHF.
2. The integrated circuit chip of claim 1 , wherein the total size of the MEMS device is less than 10000 um2.
3. The integrated circuit chip of claim 1 further comprising a set of at least three springs distributed evenly around the MEMS device and rotated around a central axis of the MEMS device.
4. The integrated circuit chip of claim 3 , wherein the device shape is round and the springs have a spiral shape.
5. The integrated circuit chip of claim 4 , wherein the springs are made with one of a single metal layer and a stack-up of at least two metal layers.
6. The integrated circuit chip of claim 5 , wherein the MEMS device is an inertial sensor.
7. The integrated circuit chip of claim 6 comprising a proof mass, wherein the proof mass is made with a stack-up of four metal layers and the springs, wherein the springs are one of: made and connected with a top metal layer of the proof mass forming the stack-up and connected with two top metal layers of the stack-up.
8. The integrated circuit chip of claim 6 , wherein the springs are connected to an external ring such that a portion thereof remains buried into a silicon oxide on its outer edge after the vHF etching.
9. The integrated circuit chip of claim 1 , wherein the MEMS device has a top metal plane and a bottom metal plane that is smaller than the top one.
10. The integrated circuit chip of claim 9 , wherein an outer ring width of the bottom metal plane is less than or equal to 10% to 50% the width of an outer ring of the top metal plane.
11. The integrated circuit chip of claim 1 , wherein the integrated circuit includes an application-specific integrated circuit (ASIC).
12. The integrated circuit chip of claim 1 , wherein pad includes a plurality of metal layers other than the top metal layer, at least one of the plurality of metal layers other than the top metal layer being arranged to extend laterally beyond the vertically aligned passivation opening in all directions.
13. The integrated circuit chip of claim 1 , wherein the metal filling structures have random shapes.
14. The integrated circuit chip of claim 1 , wherein a plurality of springs are distributed evenly around the MEMS device so that the MEMS device cannot be tilted after being released by the post-processing of vHF.