Granted Patent B2

US 12,381,041 · App. 18/297,057 · Granted Aug 5, 2025

Inventors: Larry Buffle (Grenoble, FR); Frédéric Voiron (Barraux, FR); Julien El Sabahy (Grenoble, FR); Brigitte Soulier (Grenoble, FR)

Assignee: MURATA MANUFACTURING CO., LTD.

H01G4/33H01G4/012H01G4/10H10D1/042H10D1/714H10D1/716H01G4/085

Abstract

Claims (27)

1. An electrical device comprising a capacitor, comprising:

a substrate;

an anodic porous oxide region above the substrate having a top surface;

a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region from its top surface, the first capacitor electrode region having a first wall perpendicular to the top surface; and

a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region from its top surface, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region,

the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region so that a capacitor is formed by the first capacitor electrode region, the second capacitor electrode region, and the dielectric portion,

wherein the dielectric portion further comprises a filling material inside at least a group of pores of the part of the anodic porous oxide region comprised in the dielectric portion.

2. The electrical device according to claim 1 , wherein the first capacitor electrode region comprises two substantially parallel first walls respectively facing two substantially parallel second walls of the second capacitor electrode region, and wherein the dielectric portion extends between each first wall of the first capacitor electrode region and each second wall of the second capacitor electrode region which are facing.

3. The electrical device according to claim 2 , wherein the first capacitor electrode region and the second capacitor electrode region are arranged in an interlocking-comb structure or an interlocking spiral structure.

4. The electrical device of claim 1 , wherein the filling material is arranged in all the pores of the part of the anodic porous oxide region comprised in the dielectric portion.

5. The electrical device of claim 1 , wherein at least one pore of the part of the anodic porous oxide region comprised in the dielectric portion is not filled with the filling material.

6. The electrical device of claim 1 , wherein the filling material is a dielectric material, or the filling material is a high-K dielectric, or the filling material is a low-K dielectric.

7. The electrical device of claim 1 , further comprising a conductive pattern arranged between the substrate and the anodic porous region and/or between the substrate and the first capacitor electrode region or the second capacitor electrode region.

8. The electrical device of claim 7 , wherein the conductive pattern is arranged only between the substrate and one capacitor electrode region selected between the first and the second, and the conductive pattern is electrically connected to a same electrical potential as this selected capacitor electrode region.

9. The electrical device of claim 1 , comprising at least two of said capacitors, the at least two of said capacitors having a different capacitance value, and/or a different breakdown voltage value.

10. The electrical device of claim 1 , wherein the anodic porous oxide region has a thickness above 3 micrometers.

11. The electrical device of claim 1 , wherein the dielectric portion has a width measured from the first wall of the first capacitor electrode region to the second wall of the second capacitor electrode region above 500 nanometers.

12. A method for manufacturing an electrical device comprising a capacitor, the method comprising:

providing an anodizable layer above a substrate;

anodizing at least a portion of the anodizable layer so as to obtain an anodic porous oxide region having a top surface;

forming a first cavity extending in the anodic porous oxide region from its top surface so as to define a first cavity wall perpendicular to the top surface;

forming a second cavity extending in the anodic porous oxide region from its top surface so as to define a second cavity wall perpendicular to the top surface and facing the first cavity wall of the first cavity;

filling at least partially the first cavity with an electrically conductive material so as to obtain a first capacitor electrode region arranged in the anodic porous oxide region having a first wall perpendicular to the top surface; and

filling at least partially the second cavity with an electrically conductive material so as to obtain a first capacitor electrode region arranged in the anodic porous oxide region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region,

the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region so that a capacitor is formed by the first capacitor electrode region, the second capacitor electrode region, and the dielectric portion, and

further comprising filling, with a filling material, at least a group of pores of the anodic porous oxide region separating the first wall of the first capacitor electrode region from the second wall of the second capacitor electrode region.

13. The method according to claim 12 , wherein the filling comprises an atomic layer deposition step.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (15)