Epitaxial source/drain feature with enlarged lower section interfacing with backside via
A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.
1. A semiconductor structure, comprising:
an isolation structure;
first and second source/drain (S/D) features over the isolation structure in a vertical direction, defining a first horizontal direction from the first S/D feature to the second S/D feature from a top view;
one or more channel layers connecting the first and the second S/D features;
a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and
a via structure under the first S/D feature and electrically connecting to the first S/D feature,
wherein, in a cross-sectional view defined by the vertical direction and a second horizontal direction perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.
2. The semiconductor structure of claim 1 , further comprising:
a S/D contact disposed over and connecting to the first S/D feature.
3. The semiconductor structure of claim 1 , further comprising a silicide feature between the first S/D feature and the via structure.
4. The semiconductor structure of claim 1 , further comprising a dielectric feature directly under the second S/D feature and contacting the second S/D feature.
5. The semiconductor structure of claim 4 , further comprising a S/D contact over the second S/D feature and electrically connecting to the second S/D feature.
6. The semiconductor structure of claim 1 , further comprising two dielectric fins adjacent to sidewalls of the first S/D feature.
7. The semiconductor structure of claim 6 , wherein the via structure extends directly below at least one of the dielectric fins.
8. The semiconductor structure of claim 1 , wherein the one or more channel layers include a stack of semiconductor layers, and the gate structure wraps around each of the stack of semiconductor layers.
9. The semiconductor structure of claim 1 , wherein the via structure is wider than the first S/D feature in the cross-sectional view.
10. A semiconductor structure, comprising:
an isolation structure;
a source/drain (S/D) feature over the isolation structure;
one or more channel layers connected to the S/D feature;
a gate structure engaging the one or more channel layers;
a via directly under the S/D feature and electrically connecting to the S/D feature; and
a S/D contact disposed on the S/D feature opposite from the via;
wherein, in a cross-sectional view parallel to a lengthwise direction of the gate structure, the via has a profile that becomes wider from a bottom surface to a middle portion and then becomes narrower from the middle portion to a top surface.
11. The semiconductor structure of claim 10 , wherein a widest part of the middle portion has a width in a range of 40 nm to 90 nm.
12. The semiconductor structure of claim 10 , wherein the middle portion extends beyond the top surface by a lateral distance in a range of 5 nm to 25 nm on both sides in the cross-sectional view.
13. The semiconductor structure of claim 10 , further comprising two dielectric fins sandwiching the S/D feature, wherein the via extends directly below at least one of the dielectric fins from a top view.
14. The semiconductor structure of claim 10 , further comprising a power rail below the via and electrically connected to the via.
15. The semiconductor structure of claim 14 , wherein the S/D feature is a first S/D feature, further comprising a second S/D feature over the isolation structure, wherein the one or more channel layers connect the first and the second S/D features, wherein the second S/D feature is electrically isolated from the power rail.
16. A semiconductor structure, comprising:
an isolation structure;
two dielectric fins over the isolation structure;
a source/drain (S/D) feature over the isolation structure and between the two dielectric fins;
one or more semiconductor channel layers connected to the S/D feature and lengthwise parallel to the two dielectric fins; and
a via directly under the S/D feature and electrically connected to the S/D feature,
wherein, in a cross-sectional view perpendicular to the lengthwise direction of the two dielectric fins, the via has a profile that has a middle portion wider than both a top surface and a bottom surface of the via, and wherein the isolation structure laterally surrounds side surfaces of the via.
17. The semiconductor structure of claim 16 , wherein the via extends laterally directly below at least one of the dielectric fins.
18. The semiconductor structure of claim 16 , further comprising a power rail below the via and the isolation structure and electrically connected to the via.
19. The semiconductor structure of claim 16 , wherein:
the two dielectric fins are separated from one another by a first horizontal direction;
the two dielectric fins are disposed over the isolation structure by a vertical direction; and
the cross-sectional view is defined by the first horizontal direction and the vertical direction.
20. The semiconductor structure of claim 16 , further comprising a silicide material disposed between the via and the S/D feature.