IP Library Granted Patent US 12,469,708
Granted Patent B2
US 12,469,708 · App. 18/304,059 · Granted Nov 11, 2025

Barrier layer for contact structures of semiconductor devices

Inventors: Hsin-Hsiang Tseng (Changhua County, TW); Chi-Ruei Yeh (New Taipei, TW); Tsung-Yu Chiang (New Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/28518H01L21/32133H10D30/024H10D30/6211H10D30/6219H10D64/62
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Quick Facts
Patent No.
US 12,469,708
App. No.
18/304,059
Granted
Nov 11, 2025
Kind
B2
Abstract

The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

Claims (54)

1 . A method, comprising:

forming a source/drain (S/D) region on a fin structure;

forming, on the S/D region, a S/D contact structure comprising a first metal and a glue layer;

forming, on the S/D contact structure, a barrier layer that comprises silicon and the first metal, wherein the barrier layer is in physical contact with a sidewall surface of the glue layer; and

forming, on the barrier layer, a via contact structure comprising a second metal different from the first metal, wherein the barrier layer blocks a diffusion of the first metal in the S/D contact structure to the via contact structure.

2 . The method of claim 1 , wherein the forming the barrier layer comprises:

implanting a top portion of the S/D contact structure with silicon; and

annealing the S/D contact structure to form the barrier layer.

3 . The method of claim 1 , wherein the forming the barrier layer comprises:

treating the S/D contact structure with a silicon-containing gas; and

annealing the treated S/D contact structure to form the barrier layer.

4 . The method of claim 1 , wherein the forming the barrier layer comprises:

depositing a semiconductor layer comprising silicon on the S/D contact structure;

depositing an additional glue layer on the semiconductor layer;

depositing a cap layer on the additional glue layer; and

annealing the semiconductor layer and the S/D contact structure to form the barrier layer.

5 . The method of claim 4 , further comprising diffusing a dopant in the semiconductor layer into the barrier layer.

6 . The method of claim 4 , further comprising removing the cap layer, the additional glue layer, and the semiconductor layer.

7 . The method of claim 1 , wherein the forming the via contact structure comprises:

etching a portion of the barrier layer to form a concave top surface of the barrier layer; and

forming the via contact structure on the concave top surface.

8 . The method of claim 7 , wherein the forming the via contact structure further comprises:

implanting the concave top surface of the barrier layer with silicon; and

annealing the barrier layer implanted with silicon.

9 . The method of claim 1 , wherein the forming the via contact structure comprises:

depositing an etch stop layer on the barrier layer;

depositing an interlayer dielectric (ILD) layer on the etch stop layer;

etching the ILD layer and the etch stop layer over the barrier layer to form a first opening;

etching a portion of the barrier layer to form a second opening having a concave top surface, wherein the second opening is connected to the first opening and has a diameter greater than the first opening; and

forming the via contact structure in the first and second openings.

10 . The method of claim 1 , wherein the forming the via contact structure comprises:

depositing an etch stop layer on the barrier layer;

depositing an interlayer dielectric (ILD) layer on the etch stop layer;

etching the ILD layer and the etch stop layer over the barrier layer to form an opening; and

forming the via contact structure in the opening.

11 . A semiconductor device, comprising:

a source/drain (S/D) region on a fin structure;

a S/D contact structure on the S/D region, wherein the S/D contact structure comprises a metal and a glue layer;

a barrier layer on the S/D contact structure and in physical contact with a sidewall surface of the glue layer, wherein the barrier layer comprises silicon and the metal; and

a via contact structure on the barrier layer, wherein the barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

12 . The semiconductor device of claim 11 , wherein the barrier layer comprises a dopant.

13 . The semiconductor device of claim 11 , wherein the via contact structure comprises a first portion in the barrier layer and a second portion above the barrier layer, and wherein a diameter of the first portion is greater than that of the second portion.

14 . The semiconductor device of claim 11 , wherein the via contact structure comprises an additional metal different from the metal in the S/D contact structure.

15 . The semiconductor device of claim 11 , wherein the barrier layer comprises cobalt monosilicide and cobalt disilicide, and wherein a concentration of the cobalt monosilicide is greater than that of the cobalt disilicide.

16 . A semiconductor device, comprising:

a source/drain (S/D) region on a fin structure;

a S/D contact structure on the S/D region, wherein the S/D contact structure comprises a metal and a glue layer;

a barrier layer on the S/D contact structure and comprising silicon and the metal, wherein top surfaces of the glue layer and the barrier layer are coplanar;

a dielectric layer on the top surfaces of the glue layer and barrier layer; and

a via contact structure extending through the dielectric layer and in contact with the barrier layer, wherein the barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

17 . The semiconductor device of claim 16 , wherein the barrier layer comprises a dopant.

18 . The semiconductor device of claim 16 , wherein the via contact structure comprises a first portion in the barrier layer and a second portion in the dielectric layer, and wherein a diameter of the first portion is greater than that of the second portion.

19 . The semiconductor device of claim 16 , wherein the via contact structure comprises an additional metal different from the metal in the S/D contact structure.

20 . The semiconductor device of claim 16 , wherein the barrier layer comprises cobalt monosilicide and cobalt disilicide, and wherein a concentration of the cobalt monosilicide is greater than that of the cobalt disilicide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2025
From: TSENG, HSIN-HSIANG; YEH, CHI-RUEI; CHIANG, TSUNG-YU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 072567/0917 →
Continuity (2)
Division 17081738 · Oct 27, 2020
Related Publication 20230260792A1 · Aug 17, 2023
References Cited (18)
US 9105490B2 · Wang et al. · 2015 [cited by applicant]
US 9236267B2 · De et al. · 2016 [cited by applicant]
US 9236300B2 · Liaw · 2016 [cited by applicant]
US 9406804B2 · Huang et al. · 2016 [cited by applicant]
US 9443769B2 · Wang et al. · 2016 [cited by applicant]
US 9520482B1 · Chang et al. · 2016 [cited by applicant]
US 9548366B1 · Ho et al. · 2017 [cited by applicant]
US 9576814B2 · Wu et al. · 2017 [cited by applicant]
US 9831183B2 · Lin et al. · 2017 [cited by applicant]
US 9859386B2 · Ho et al. · 2018 [cited by applicant]
US 10964792B1 · Cheng · 2021 [cited by examiner]
US 11069784B2 · Tsai · 2021 [cited by examiner]
US 11532561B2 · Lin · 2022 [cited by examiner]
US 20070181954A1 · Oikawa · 2007 [cited by applicant]
US 20100013029A1 · Chuang et al. · 2010 [cited by applicant]
US 20180254246A1 · Park et al. · 2018 [cited by applicant]
US 20190304833A1 · Chen et al. · 2019 [cited by applicant]
US 20220005934A1 · Park et al. · 2022 [cited by applicant]