Packaged interconnect structures
Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
1 . A method, comprising:
forming a plurality of interconnect structure packages,
wherein each of the plurality of interconnect structure packages comprises a plurality of interconnect structures;
attaching the plurality of interconnect structure packages to a carrier substrate;
attaching a semiconductor die package to the carrier substrate such that the plurality of interconnect structure packages are adjacent to one or more sides of the semiconductor die package; and
forming an encapsulation layer around the plurality of interconnect structure packages and around the semiconductor die package,
wherein forming the plurality of interconnect structure packages comprises:
forming a plurality of recesses in a silicon substrate;
forming a plurality of through silicon via (TSV) structures in the plurality of recesses;
dicing the silicon substrate into the plurality of interconnect structure packages after forming the plurality of TSV structures; and
forming, for an interconnect structure package of the plurality of interconnect structure packages, a plurality of conductive connection structures prior to dicing the silicon substrate into the plurality of interconnect structure packages,
wherein the plurality of conductive connection structures are formed on a subset of TSV structures of the plurality of TSV structures associated with the interconnect structure package.
2 . The method of claim 1 , wherein forming the plurality of interconnect structure packages further comprises:
forming an oxide liner in the plurality of recesses such that sidewalls and bottom surfaces of the plurality of recesses are lined with the oxide liner,
wherein the plurality TSV structures are formed in the plurality of recesses over the oxide liner.
3 . The method of claim 1 , wherein forming the plurality of interconnect structure packages further comprises:
forming, for the interconnect structure package, a polymer layer around the plurality of conductive connection structures prior to dicing the silicon substrate into the plurality of interconnect structure packages; and
wherein attaching the plurality of interconnect structure packages to the carrier substrate comprises:
placing the interconnect structure package on a die attach film that is over the carrier substrate.
4 . The method of claim 3 , wherein a release layer is formed between the carrier substrate and the die attach film.
5 . The method of claim 1 ,
wherein attaching the plurality of interconnect structure packages to the carrier substrate comprises:
placing the plurality of conductive connection structures, of the interconnect structure package, into a die attach film that is over the carrier substrate such that the plurality of conductive connection structures are submerged in the die attach film.
6 . The method of claim 1 , wherein forming the interconnect structure package further comprises performing an annealing operation after forming the plurality of TSV structures to reflow the plurality of TSV structures.
7 . The method of claim 1 , wherein forming the interconnect structure package further comprises performing an annealing operation after forming the plurality of conductive connection structures to reflow the plurality of conductive connection structures.
8 . A method, comprising:
forming an interconnect structure package;
attaching the interconnect structure package to a carrier substrate,
wherein the interconnect structure package comprises a plurality of interconnect structures, and
wherein attaching the interconnect structure package to the carrier substrate comprises securing the interconnect structure package to a die attach film formed on the carrier substrate;
securing a semiconductor die package to the die attach film,
wherein the semiconductor die package is adjacent to a side of the interconnect structure package; and
forming an encapsulation layer around the interconnect structure package and around the semiconductor die package;
wherein forming the interconnect structure package comprises:
forming a release layer on an additional carrier substrate;
forming the plurality of interconnect structures on the release layer; and
depositing an additional encapsulation layer on the release layer and around the plurality of interconnect structures.
9 . The method of claim 8 , wherein forming the interconnect structure package further comprises:
forming a plurality of conductive structures on the plurality of interconnect structures; and
depositing a polymer layer on the plurality of conductive structures.
10 . The method of claim 9 , wherein forming the interconnect structure package further comprises performing an annealing operation after forming the plurality of conductive structures to reflow the plurality of conductive structures.
11 . The method of claim 8 , wherein the additional encapsulation layer comprises a molding compound.
12 . The method claim 8 , further comprising forming a redistribution structure over the interconnect structure package, semiconductor die package, and the encapsulation layer.
13 . A method, comprising:
forming a plurality of interconnect structure packages;
mounting the plurality of interconnect structure packages on a carrier substrate,
wherein the plurality of interconnect structure packages comprise a plurality of interconnect structures;
mounting a semiconductor die package on the carrier substrate adjacent to at least one of the plurality of interconnect structure packages;
depositing an encapsulation layer around the plurality of interconnect structure packages and the semiconductor die package; and
forming a redistribution structure over the plurality of interconnect structure packages, semiconductor die package, and the encapsulation layer,
wherein forming the plurality of interconnect structure packages comprises:
etching a semiconductor substrate to form a plurality of recesses in the semiconductor substrate;
depositing conductive material in the plurality of recesses to form the plurality of interconnect structures;
forming a plurality of connection structures on the plurality of interconnect structures; and
dicing the semiconductor substrate into the plurality of interconnect structure packages after forming the plurality of connection structures.
14 . The method of claim 13 , wherein the redistribution structure comprises a plurality of metallization structures connected to the plurality of interconnect structures.
15 . The method of claim 13 ,
wherein forming the plurality of interconnect structure packages further comprises:
depositing a liner layer on sidewalls and bottom surfaces of the plurality of recesses,
wherein the conductive material is deposited in the plurality of recesses on the liner layer.
16 . The method of claim 13 , wherein mounting the plurality of interconnect structure packages on the carrier substrate and mounting the semiconductor die package on the carrier substrate comprises submerging at least a portion of the plurality of interconnect structure packages and at least a portion of the semiconductor die package in a die attach film, and
wherein the die attach film is on the carrier substrate.
17 . The method of claim 1 , wherein the die attach film is in one of a semi-liquid state or a liquid state when at least the portion of the plurality of interconnect structure packages and at least the portion of the semiconductor die package are submerged in the die attach film.
18 . The method of claim 13 , wherein forming the plurality of interconnect structure packages further comprises forming a polymer layer around the plurality of connection structures prior to dicing the semiconductor substrate into the plurality of interconnect structure packages.
19 . The method of claim 13 , wherein forming the plurality of interconnect structure packages further comprises performing an annealing operation after forming the plurality of interconnect structures to reflow the plurality of interconnect structures.
20 . The method of claim 13 , wherein mounting the plurality of interconnect structure packages on the carrier substrate comprises adhering the plurality of interconnect structure packages to the carrier substrate through a die attach film.