Semiconductor package
A semiconductor package includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and a second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.
1 . A semiconductor package comprising:
a buffer die;
semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and at least one second semiconductor chip on the plurality of first semiconductor chips; and
a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks,
wherein each of the plurality of first semiconductor chips and the at least one second semiconductor chip includes:
a wiring part including multilayer wirings;
an upper connection structure on the wiring part and having a plurality of upper conductive pads; and
a lower connection structure under the wiring part and having a plurality of lower conductive pads, and
wherein the at least one second semiconductor chip further includes:
a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer;
wherein the redistribution layer further includes a redistribution via in the insulating layer and connected to one of the plurality of redistribution pads thereunder, and
wherein in a corresponding semiconductor chip stack of the semiconductor chip stacks, a number of the redistribution layer is equal to a number of the at least one second semiconductor chip in the corresponding semiconductor chip stack.
2 . The semiconductor package of claim 1 , wherein the upper connection structure includes:
a first passivation layer covering an upper surface of the wiring part and having the plurality of upper conductive pads therein; and
first conductive pads provided on the plurality of upper conductive pads within the first passivation layer and having a recessed upper region.
3 . The semiconductor package of claim 2 , wherein the insulating layer of the redistribution layer fills the recessed upper region and covers the first conductive pads and the first passivation layer.
4 . The semiconductor package of claim 3 , wherein the plurality of redistribution pads are in contact with the first conductive pads.
5 . A semiconductor package comprising:
a buffer die;
semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and at least one second semiconductor chip on the plurality of first semiconductor chips;
dummy pads; and
a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks,
wherein each of the plurality of first semiconductor chips and the at least one second semiconductor chip includes:
a wiring part including multilayer wirings;
an upper connection structure on the wiring part and having a plurality of upper conductive pads; and
a lower connection structure under the wiring part and having a plurality of lower conductive pads,
wherein the at least one second semiconductor chip further includes:
a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer,
wherein the upper connection structure includes:
a first passivation layer covering an upper surface of the wiring part and having the plurality of upper conductive pads therein; and
first conductive pads provided on the plurality of upper conductive pads within the first passivation layer and having a recessed upper region,
wherein the dummy pads are between the first conductive pads in the first passivation layer, and
wherein the dummy pads are on a same level as the first conductive pads.
6 . A semiconductor package comprising:
a buffer die;
semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and at least one second semiconductor chip on the plurality of first semiconductor chips; and
a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks,
wherein each of the plurality of first semiconductor chips and the at least one second semiconductor chip includes:
a wiring part including multilayer wirings;
an upper connection structure on the wiring part and having a plurality of upper conductive pads; and
a lower connection structure under the wiring part and having a plurality of lower conductive pads,
wherein the at least one second semiconductor chip further includes:
a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer,
wherein the upper connection structure includes:
a first passivation layer covering an upper surface of the wiring part and having the plurality of upper conductive pads therein; and
first conductive pads provided on the plurality of upper conductive pads within the first passivation layer and having a recessed upper region,
wherein the redistribution layer further includes a redistribution via in the insulating layer and connected to the plurality of redistribution pads thereunder, and
wherein a lower end of the redistribution via is at a level lower than an upper end of the first conductive pads.
7 . The semiconductor package of claim 1 , wherein each of the semiconductor chip stacks includes two or more first semiconductor chips.
8 . The semiconductor package of claim 1 , wherein each of the semiconductor chip stacks includes a same number of the plurality of first semiconductor chips as each other.
9 . The semiconductor package of claim 1 , further comprising an uppermost semiconductor chip stack stacked on the semiconductor chip stacks and including at least one first semiconductor chip,
wherein an upper surface of the uppermost semiconductor chip stack is coplanar with an upper surface of the mold layer.
10 . The semiconductor package of claim 1 , wherein a thickness of one of the plurality of first semiconductor chips is 20 μm to 25 μm, and
wherein a thickness of one of the at least one second semiconductor chip is 30 μm to 40 μm.
11 . The semiconductor package of claim 1 , wherein a thickness of the redistribution layer is 10 μm to 15 μm.
12 . The semiconductor package of claim 1 , wherein the insulating layer of the redistribution layer includes at least one of silicon oxide (SiO 2 ) and silicon carbonitride (SiCN).
13 . The semiconductor package of claim 1 , wherein the plurality of redistribution pads include copper (Cu).
14 . The semiconductor package of claim 5 ,
wherein each of the semiconductor chip stacks includes a same number of the plurality of first semiconductor chips as each other.
15 . The semiconductor package of claim 6 ,
wherein each of the semiconductor chip stacks includes a same number of the plurality of first semiconductor chips as each other.
16 . The semiconductor package of claim 5 , wherein the insulating layer of the redistribution layer fills the recessed upper region and covers the first conductive pads and the first passivation layer.
17 . The semiconductor package of claim 16 , wherein the plurality of redistribution pads are in contact with the first conductive pads.
18 . The semiconductor package of claim 1 , wherein the upper connection structure includes:
a first passivation layer covering an upper surface of the wiring part and having an upper conductive pad among the plurality of upper conductive pads therein; and
first conductive pads on the upper conductive pad in the first passivation layer and having a recessed upper region.
19 . The semiconductor package of claim 5 , wherein the redistribution layer further includes a redistribution via in the insulating layer and connected to one of the plurality of redistribution pads thereunder, and
wherein a lower end of the redistribution via is at a level lower than an upper end of one of the plurality of upper conductive pads.
20 . The semiconductor package of claim 1 , wherein the buffer die includes an interposer or a logic circuit chip.