Memory device adjusting duty cycle and memory system having the same
A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
1. An apparatus comprising:
a first duty cycle adjustor configured to perform a first duty adjust operation to adjust a first clock based on first monitoring information;
a second duty cycle adjustor configured to perform a second duty adjust operation to adjust a second clock based on second monitoring information;
a duty cycle monitor coupled to the first duty cycle adjustor and the second duty cycle adjustor, configured to monitor the first clock and the second clock, configured to generate the first monitoring information based on a result of monitoring the first clock, and configured to generate the second monitoring information based on a result of monitoring the second clock; and
a controller configured to determine a duty state of the first clock and a duty state of the second clock, wherein the first duty adjust operation and the second duty adjust operation are performed in response to an enable signal.
2. The apparatus of claim 1 , further comprising a clock tree configured to generate the first clock and the second clock.
3. The apparatus of claim 1 , wherein the controller generates a first control signal and provides the first control signal to the first duty cycle adjustor, and generates a second control signal and provides the second control signal to the second duty cycle adjustor.
4. The apparatus of claim 3 , wherein the first control signal includes first polarity information, and the second control signal includes second polarity information.
5. The apparatus of claim 1 , further comprising a mode register configured to store the first monitoring information and the second monitoring information.
6. The apparatus of claim 1 , further comprising a flip-flop configured to latch write data and/or read data.
7. An apparatus comprising:
a first duty cycle adjustor configured to adjust a first clock based on first monitoring information;
a second duty cycle adjustor configured to adjust a second clock based on second monitoring information;
a duty cycle monitor configured to monitor a duty cycle of the first clock and a duty cycle of the second clock, and configured to generate the first monitoring information and the second monitoring information; and
a controller configured to generate a first control signal and provide the first control signal to the first duty cycle adjustor, and to generate a second control signal and provide the second control signal to the second duty cycle adjustor, wherein the first control signal includes first polarity information, and the second control signal includes second polarity information.
8. The apparatus of claim 7 , further comprising a clock tree configured to generate the first clock and the second clock.
9. The apparatus of claim 7 , further comprising a mode register configured to store the first monitoring information and the second monitoring information.
10. The apparatus of claim 9 , wherein the mode register stores mode register information for a setting operation within a memory device that includes the first duty cycle adjustor, the second duty cycle adjustor and the duty cycle monitor.
11. The apparatus of claim 7 , further comprising a flip-flop configured to latch write data and/or read data.
12. The apparatus of claim 7 , wherein the controller determines a duty state of the first clock and a duty state of the second clock.
13. The apparatus of claim 7 , wherein the first duty cycle adjustor performs the adjust of the first clock and the second duty cycle adjustor performs the adjust of the second clock, in response to an enable signal.
14. An apparatus comprising:
a first duty cycle adjustor configured to perform a first duty adjust operation to adjust a first clock based on first monitoring information;
a second duty cycle adjustor configured to perform a second duty adjust operation to adjust a second clock based on second monitoring information;
a duty cycle monitor coupled to the first duty cycle adjustor and the second duty cycle adjustor, configured to monitor the first clock and the second clock, configured to generate the first monitoring information based on a result of monitoring the first clock, and configured to generate the second monitoring information based on a result of monitoring the second clock; a mode register configured to store the first monitoring information and the second monitoring information; and
a controller configured to check the first monitoring information and the second monitoring information, and to output one or more control signals, based on the first monitoring information and/or the second monitoring information.
15. The apparatus of claim 14 , further comprising a flip-flop configured to latch write data and/or read data.
16. The apparatus of claim 14 , wherein the controller determines a duty state of the first clock and a duty state of the second clock.
17. The apparatus of claim 14 , further comprising a clock tree configured to generate the first clock and the second clock.
18. The apparatus of claim 14 , wherein the controller generates a first control signal and provides the first control signal to the first duty cycle adjustor, and generates a second control signal and provides the second control signal to the second duty cycle adjustor.
19. The apparatus of claim 18 , wherein the first control signal includes first polarity information, and the second control signal includes second polarity information.
20. The apparatus of claim 14 , wherein the first duty adjust operation and the second duty adjust operation are performed in response to an enable signal.