Memory device adjusting duty cycle and memory system having the same
A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
1 . A method for performing a duty adjustment operation in a SDRAM device, the method comprising:
receiving, from an external device, a write clock and a control command;
generating an internal write clock based on the write clock;
performing a duty monitoring operation on the internal write clock in response to the control command for generating a duty monitoring information;
storing the duty monitoring information in a first mode register set (MRS);
transmitting the duty monitoring information to the external device;
receiving a duty control information which is generated based on the duty monitoring information;
storing the duty control information in a second MRS of the SDRAM device; and
performing the duty adjustment operation on the internal write clock using the duty control information stored in the second MRS for generating a duty adjusted internal write clock,
wherein the duty control information includes a polarity of a duty cycle adjustment which indicates whether to increase a portion of logic level high of the internal write clock or to increase a portion of logic level low of the internal write clock.
2 . The method of claim 1 , wherein the duty control information includes a duty cycle adjustment weight with which an amount of duty adjustment of the internal write clock is adjusted.
3 . The method of claim 1 , wherein the duty monitoring information comprises a first mode register set, and at least one field of the first mode register set indicates whether the logic high portion of the internal write clock is wider than the logic low portion of the internal write clock.
4 . The method of claim 3 , wherein the duty monitoring information indicates duty cycle error of the write clock, and is used for adjusting duty cycle error of the write clock.
5 . The method of claim 4 , wherein the duty control information includes a period of the duty monitoring operation of the SDRAM memory device based on the duty monitoring information.
6 . The method of claim 5 , wherein the duty control information increases the period of the duty monitoring operation when the duty monitoring information indicates that the duty cycle error of the write clock is within a predetermined range.
7 . The method of claim 5 , wherein the duty control information temporarily disables the duty monitoring operation when the duty monitoring information indicates that the duty cycle error of the write clock is within a predetermined range.
8 . The method of claim 1 , wherein transmitting the duty monitoring information is performed by a mode register set (MRS) read operation.
9 . The method of claim 8 , wherein the MRS read operation includes reading the first mode register set corresponding to the duty monitoring information.
10 . The method of claim 9 , wherein at least one field of the first mode register set indicates whether the logic high portion of an internal write clock generated from the write clock is wider than the logic low portion of the internal write clock.
11 . A memory controller comprising:
a plurality of data transmitters configured to generate write data to an external source;
a write clock transmitter configured to generate a write clock to the external source in synchronization with the write data; and
a duty controller configured to:
receive, from the external source, first duty monitoring information which represents a result of monitoring a duty of the write clock, and generate a first duty control information based on the first duty monitoring information, the first duty control information being used to adjust a duty cycle of an internal write clock generated from the write clock; and
receive, from the external source, second duty monitoring information which represents a result of monitoring a duty of a read clock generated based on the write clock, and generate a second duty control information based on the second duty monitoring information, the second duty control information being used to adjust the duty cycle of the read clock,
wherein the first duty control information further includes a polarity of the duty cycle adjustment with which the memory controller decides whether to increase a portion of logic level high of the internal write clock or to increase a portion of logic level low of the internal write clock.
12 . The memory controller of claim 11 , wherein the first duty control information includes a duty cycle adjustment weight with which the external source controls amount of duty adjustment of the internal write clock.
13 . The memory controller of claim 11 , wherein the memory controller receives the first duty monitoring information from a first mode register set of the external source, and at least one field of the first mode register set indicates whether the logic high portion of the internal write clock is wider than the logic low portion of the internal write clock.
14 . The memory controller of claim 11 , wherein the memory controller controls a period of duty monitoring operation based on the first duty monitoring information.
15 . The memory controller of claim 14 , wherein the memory controller increases the period of the duty monitoring operation when the first duty monitoring information indicates that a duty cycle error of the write clock is within a predetermined range.
16 . The memory controller of claim 14 , wherein the memory controller temporarily disables the duty monitoring operation when the first duty monitoring information indicates that a duty cycle error of the write clock is within a predetermined range.
17 . The memory controller of claim 11 , wherein the memory controller is implemented in a system on chip (SoC).
18 . The memory controller of claim 17 , wherein the SoC comprises a plurality of processing units and a volatile memory.
19 . The memory controller of claim 18 , wherein the SoC further comprises a non-volatile memory.
20 . The memory controller of claim 11 , wherein the memory controller receives the first and second duty monitoring information through a mode register set (MRS) read operation.