Semiconductor device capable of releasing process charge, and method for manufacturing the same
View Patent ↗A semiconductor device includes a first transistor, a first via contact, a second transistor and a second via contact. The first transistor includes a channel and a gate electrode. The first via contact is disposed on the gate electrode of the first transistor, and corresponds in position to the channel of the first transistor. The second transistor includes a channel and a gate electrode. The second via contact is disposed on the gate electrode of the second transistor, and corresponds in position to the channel of the second transistor. A distance between the second via contact and the channel of the second transistor is smaller than a distance between the first via contact and the channel of the first transistor.
1 . A semiconductor device comprising:
a first transistor including a channel and a gate electrode;
a first via contact disposed on the gate electrode of the first transistor, and corresponding in position to the channel of the first transistor;
a second transistor substantially coplanar with the first transistor, and including a channel and a gate electrode; and
a second via contact disposed on the gate electrode of the second transistor, and corresponding in position to the channel of the second transistor;
wherein a distance between the second via contact and the channel of the second transistor is smaller than a distance between the first via contact and the channel of the first transistor.
2 . The semiconductor device according to claim 1 , wherein the distance between the second via contact and the channel of the second transistor is smaller than half the distance between the first via contact and the channel of the first transistor.
3 . The semiconductor device according to claim 1 , wherein the gate electrode of the second transistor includes a material selected from nitride, boron, fluorine, and combinations thereof.
4 . The semiconductor device according to claim 1 , wherein the gate electrode of the second transistor includes a material selected from oxygen, argon, krypton, helium, and combinations thereof.
5 . A method for manufacturing a semiconductor device, comprising:
forming a first transistor and a second transistor, each of which includes a channel and a gate electrode;
forming a dielectric layer on the first transistor and the second transistor;
performing doping treatment on an upper portion of the gate electrode of the second transistor; and
forming a first via contact in the dielectric layer, and forming a second via contact in the dielectric layer and in the gate electrode of the second transistor, the first via contact corresponding in position to the channel of the first transistor, the second via contact corresponding in position to the channel of the second transistor.
6 . The method according to claim 5 , wherein the upper portion of the gate electrode of the second transistor is treated by performing implantation.
7 . The method according to claim 6 , wherein the implantation is performed using a material selected from nitride, boron, fluorine, and combinations thereof.
8 . The method according to claim 6 , wherein the implantation is performed at room temperature.
9 . The method according to claim 5 , wherein the upper portion of the gate electrode of the second transistor is treated by performing bombardment.
10 . The method according to claim 9 , wherein the bombardment is performed using a material selected from oxygen, argon, krypton, helium, and combinations thereof.
11 . The method according to claim 9 , wherein the bombardment is performed at room temperature.
12 . The method according to claim 5 , wherein a distance between the second via contact and the channel of the second transistor is smaller than half a distance between the first via contact and the channel of the first transistor.
13 . A method for manufacturing a semiconductor device, comprising:
forming a transistor that includes a channel and a gate electrode;
forming a dielectric layer on the transistor;
performing doping treatment on an upper portion of the gate electrode; and
forming a via contact in the dielectric layer and in the gate electrode, the via contact corresponding in position to the channel.
14 . The method according to claim 13 , wherein the upper portion of the gate electrode is treated by performing implantation.
15 . The method according to claim 14 , wherein the implantation is performed using a material selected from nitride, boron, fluorine, and combinations thereof.
16 . The method according to claim 14 , wherein the implantation is performed at room temperature.
17 . The method according to claim 13 , wherein the upper portion of the gate electrode is treated by performing bombardment.
18 . The method according to claim 17 , wherein the bombardment is performed using a material selected from oxygen, argon, krypton, helium, and combinations thereof.
19 . The method according to claim 17 , wherein the implantation is performed at room temperature.
20 . The method according to claim 13 , wherein a distance between a bottom surface of the via contact and a top surface of the channel is smaller than half a distance between a top surface of the gate electrode and the top surface of the channel.