Electronic device manufacturing method
The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.
1 . A method of manufacturing a device, comprising:
forming, in a first portion of the device and on a first surface of a substrate, an array of memory cells comprising a plurality of rows and a plurality of columns;
forming, in a second portion of the device, a plurality of transistors;
forming a first plurality of trenches separating a first plurality of substrate regions of each of the plurality of rows, the first plurality of trenches having a first depth into the substrate, the forming of a first plurality of trenches comprising:
forming a first portion of each first trench, the first portion of each first trench being transverse to the first surface of the substrate and extending through the first surface of the substrate; and
forming a second portion of each first trench in contact with the first portion of each first trench, the forming a second portion of each first trench comprising forming a first insulating layer and etching a plurality of portions of the first insulating layer; and
forming a second plurality of trenches separating a second plurality of substrate regions of each of the plurality of columns, the second plurality of trenches having a second depth into the substrate that is greater than the first depth.
2 . The method according to claim 1 wherein the substrate is of substrate-on-insulator type in the second portion of the device.
3 . The method according to claim 1 , comprising:
removing, in the first portion of the device, an upper semiconductor layer of the substrate, wherein the substrate is of substrate-on-semiconductor type and the upper semiconductor layer has a first thickness; and
expanding an insulating intermediate layer of the substrate to a thickness at least equal to the first thickness of the upper semiconductor layer of the substrate, the intermediate layer comprising a first insulating material.
4 . The method according to claim 3 wherein the method comprises forming a first insulating layer on the first and second portions of the device.
5 . The method according to claim 4 wherein forming the second portion of each first trench comprises forming a first plurality of openings in the first insulating layer, and forming the first portion of each first trench, comprises:
etching the intermediate layer through the first plurality of openings; and
removing the portions of the first insulating layer in the second portion of the device, the first insulating layer comprising a second insulating material.
6 . The method according to claim 4 , comprising removing a first plurality of portions of the first insulating layer on the first portion of the device and removing a second plurality of portions of the intermediate layer and of the first insulating layer on the first plurality of trenches, the first insulating layer comprising the first insulating material.
7 . The method according to claim 5 , comprising expanding a lower layer of the substrate of semiconductor-on-insulator type.
8 . The method according to claim 7 wherein the method comprises forming a stack comprising a second layer of the first insulating material and a third layer on the first and second portions of the device comprising the second insulating material.
9 . The method according to claim 8 wherein the first insulating material is silicon oxide and the second insulating material is silicon nitride.
10 . The method according to claim 8 wherein forming the second plurality of trenches comprises:
forming a second plurality of openings in the third layer of the stack over the second plurality of trenches;
forming a plurality of cavities through the second plurality of openings; and
forming, on the first and second portions of the device and filling the plurality of cavities, of a fourth layer comprising the first insulating material.
11 . The method according to claim 10 , comprising:
removing, by chemical mechanical polishing of a plurality of portions of the fourth layer on the third layer of the stack; and
removing the third layer.
12 . The method according to claim 11 , comprising doping the substrate.
13 . The method according to claim 1 , comprising depositing a plurality of silicon strips on a plurality of second portions of each of the first trenches.
14 . A method, comprising:
forming a plurality of insulating pillars in a first region of a semiconductor substrate;
forming a semiconductor layer surrounding each of the plurality of insulating pillars in the first region;
forming a first insulating layer on the insulating pillars and the semiconductor layer;
forming a plurality of trenches in a second and a third region of the semiconductor substrate; and
forming an insulating material in each of the plurality of trenches.
15 . The method according to claim 14 , wherein the forming the plurality of insulating pillars includes:
forming a mask on a second insulating layer of the semiconductor substrate; and
etching, through openings in the mask, entirely through the second insulating layer along a first direction.
16 . The method according to claim 15 , wherein the plurality of insulating pillars each include a first portion of the mask, the first insulating layer being formed over each respective first portion of the mask.
17 . The method according to claim 16 , wherein the semiconductor layer has a first surface that is substantially coplanar with a second surface of the second insulating layer in the second region of the semiconductor substrate.
18 . The method according to claim 17 , wherein during the forming the first insulating layer, the second insulating layer in the second region of the semiconductor substrate is entirely covered by the first insulating layer.
19 . A method, comprising:
forming, on a first surface of a substrate, an array of memory cells including a plurality of rows and a plurality of columns;
forming a first plurality of trenches separating each of the plurality of rows, the forming of the first plurality of trenches including:
forming a first portion of each first trench, the first portion of each first trench extending through the first surface of the substrate; and
forming a second portion of each first trench in contact with the first portion of each first trench, the forming a second portion of each first trench including forming an insulating layer and etching a first insulating layer; and
forming a second plurality of trenches separating each of the plurality of columns.
20 . The method according to claim 19 , wherein the first plurality of trenches have a first depth into the substrate and the second plurality of trenches have a second depth into the substrate that is greater than the first depth.