Reliable programming of one-time programmable (OTP) memory during device testing
A method includes providing one or more signals to an electronic device for performing a test procedure that involves programming a One-Time Programmable (OTP) memory in the electronic device. A verification is made as to whether connection of the one or more signals to the electronic device is stable, by performing a sequence of one or more iterations, each iteration including (i) determining, from among a set of scratchpad addresses in the OTP memory, an address that is available for programming, (ii) writing a test value to the address, and then (iii) reading the test value from the address. If the read test value differs from the written test value, re-tuning of the connection of the one or more signals is initiated. Only when the connection is verified as stable by the sequence of iterations, the OTP memory is programmed in accordance with the test procedure.
1. A method for testing electronic devices, the method comprising:
providing, by a test system, one or more external signals to an electronic device for performing a test procedure that involves programming of a One-Time Programmable (OTP) memory in the electronic device;
verifying whether the one or more external signals are connected stably to the electronic device, by performing a sequence of one or more iterations, each iteration comprising:
determining, from among a set of scratchpad addresses in the OTP memory, an address that is available for programming;
writing a test value to the address, and then reading the test value from the address; and
if the read test value differs from the written test value, initiating re-tuning of a connection of the one or more external signals; and
only when the one or more external signals are verified by the sequence of iterations as connected stably to the electronic device, programming the OTP memory of the electronic device in accordance with the test procedure.
2. The method according to claim 1 , further comprising outputting a failure indication upon finding that all the scratchpad addresses have been programmed but the one or more external signals are still connected unstably.
3. The method according to claim 1 , wherein the one or more external signals comprise a clock signal that clocks at least part of the electronic device.
4. The method according to claim 1 , wherein the one or more external signals comprise a power-supply signal that powers at least part of the electronic device.
5. The method according to claim 1 , wherein programming the OTP memory comprises updating a Life-Cycle (LC) state of the electronic device in accordance with the test procedure.
6. The method according to claim 1 , wherein determining the address that is available for programming comprises scanning the scratchpad addresses of the OTP memory for an address holding an all-zeros value.
7. The method according to claim 1 , wherein determining the address that is available for programming comprises maintaining a status of the OTP memory in a memory different from the OTP memory.
8. The method according to claim 1 , wherein:
the one or more external signals are provided to the electronic device via a connection comprising (i) one or more needles for contacting the electronic device, and/or (ii) one or more spring-loaded contacts; and
verifying whether the one or more external signals are connected stably comprises verifying whether the needles and/or spring-loaded contacts are connected stably.
9. A method for testing electronic devices, the method comprising:
in an electronic device comprising a One-Time Programmable (OTP) memory, receiving from a test system one or more external signals for performing a test procedure that involves programming of the OTP memory;
verifying whether the one or more external signals are connected stably to the electronic device, by:
determining, from among a set of scratchpad addresses in the OTP memory, an address that is available for programming; and
writing a test value to the address, reading the test value from the address, and verifying whether the read test value equals the written test value;
if the one or more external signals are verified as connected stably to the electronic device, programming the OTP memory of the electronic device in accordance with the test procedure; and
if the one or more external signals are not verified as connected stably to the electronic device, outputting a failure indication.
10. The method according to claim 9 , further comprising outputting a fatal failure indication upon finding that all the scratchpad addresses have been programmed but the connection is unstable.
11. The method according to claim 9 , wherein the one or more external signals comprise a clock signal that clocks at least part of the electronic device.
12. The method according to claim 9 , wherein the one or more external signals comprise a power-supply signal that powers at least part of the electronic device.
13. The method according to claim 9 , wherein programming the OTP memory comprises updating a Life-Cycle (LC) state of the electronic device in accordance with the test procedure.
14. The method according to claim 9 , wherein determining the address that is available for programming comprises scanning the scratchpad addresses of the OTP memory for an address holding an all-zeros value.
15. An electronic device, comprising:
a One-Time Programmable (OTP) memory; and
control hardware, configured to:
receive from a test system one or more external signals for performing a test procedure that involves programming of the OTP memory;
verify whether the one or more external signals are connected stably to the electronic device is stable, by:
determining, from among a set of scratchpad addresses in the OTP memory, an address that is available for programming; and
writing a test value to the address, reading the test value from the address, and verifying whether the read test value equals the written test value;
if the one or more external signals are verified as connected stably to the electronic device, program the OTP memory in accordance with the test procedure; and
if the one or more external signals are determined not to be connected stably to the electronic device, output a failure indication.
16. The electronic device according to claim 15 , wherein the control hardware is further configured to output a fatal failure indication upon finding that all the scratchpad addresses have been programmed but the connection is unstable.
17. The electronic device according to claim 15 , wherein the one or more external signals comprise a clock signal that clocks at least part of the electronic device.
18. The electronic device according to claim 15 , wherein the one or more external signals comprise a power-supply signal that powers at least part of the electronic device.
19. The electronic device according to claim 15 , wherein, in programming the OTP memory, the control hardware is configured to update a Life-Cycle (LC) state of the electronic device in accordance with the test procedure.
20. The electronic device according to claim 15 , wherein the control hardware is configured to determine the address that is available for programming by scanning the scratchpad addresses of the OTP memory for an address holding an all-zeros value.