Semiconductor wafer test system for controlling supply of power to semiconductor wafer test apparatus and method of controlling supply of power to semiconductor wafer test apparatus
A semiconductor wafer test system for controlling the supply of power to a semiconductor wafer test apparatus is provided. The semiconductor wafer test system includes a test operating server and the semiconductor wafer test apparatus. The test operating server manages a wafer test schedule and allocates lots to a prober, which loads wafers into the semiconductor wafer test apparatus, in accordance with the wafer test schedule. The test operating server sends a mode switch request to the semiconductor wafer test apparatus in accordance with the wafer test schedule, and the semiconductor wafer test apparatus is switched to a waiting mode in response to receipt of a request to switch to the waiting mode from the test operating server, and is switched to a ready mode in response to receipt of a request to switch to the ready mode from the test operating server.
1 . A semiconductor wafer test system comprising:
a test operating server configured to manage a wafer test schedule and send a request to switch to a waiting mode or to a ready mode to a semiconductor wafer test apparatus in accordance with the wafer test schedule; and
the semiconductor wafer test apparatus configured to switch to the waiting mode in response to receipt of the request to switch to the waiting mode from the test operating server and configured to switch to the ready mode in response to receipt of the request to switch to the ready mode from the test operating server, wherein
the test operating server is configured to send the request to switch to the waiting mode when a first lot of wafers to be tested is unloaded, and send the request to switch to the ready mode before loading of a second lot of wafers to be tested.
2 . The semiconductor wafer test system of claim 1 , wherein
in the waiting mode, a supply of power to first hardware boards of the semiconductor wafer test apparatus is cut off, and a power to essential devices of the semiconductor wafer test apparatus is maintained,
the essential devices include a test management processor (TMP), a main frame interface board, and second hardware boards of a tester head, and
the second hardware boards include an algorithmic pattern generator (ALPG) board and a test head interface board.
3 . The semiconductor wafer test system of claim 1 , wherein
the semiconductor wafer test apparatus is further configured to switch to the waiting mode in response to the receipt of the request to switch sent by the test operating server when the first lot of wafers is loaded, and is further configured to switch to the ready mode in response to the receipt of the request to switch sent by the test operating server before the loading of the second lot of wafers.
4 . The semiconductor wafer test system of claim 1 , wherein
the test operating server is configured to designate an idle time based on the wafer test schedule and send the request to switch to the waiting mode during the idle time, and
the semiconductor wafer test apparatus is configured to switch to the waiting mode during the idle time in response to the receipt of the request to switch to the waiting mode during the idle time and is configured to automatically switch to the ready mode after a lapse of the idle time.
5 . The semiconductor wafer test system of claim 4 , wherein the idle time is an amount of time required for at least one of a maintenance of the semiconductor wafer test apparatus, a replacement of a probe card, and a change of a temperature condition for a wafer test.
6 . The semiconductor wafer test system of claim 4 , wherein the idle time is an interval between a start time of unloading of the first lot of wafers and a scheduled start time of the loading of the second lot of wafers in response to the interval being equal to or greater than a reference value.
7 . The semiconductor wafer test system of claim 6 , wherein the reference value is an average waiting time of the semiconductor wafer test apparatus.
8 . The semiconductor wafer test system of claim 4 , wherein
in response to the idle time being extended due to a change in the wafer test schedule, the test operating server is configured to send a request to extend a duration of the waiting mode to the semiconductor wafer test apparatus, and
the semiconductor wafer test apparatus is configured to be maintained in the waiting mode for an extended idle time in response to receipt of the request to extend the duration of the waiting mode.
9 . The semiconductor wafer test system of claim 4 , wherein
in response to the idle time being reduced due to a change in the wafer test schedule, the test operating server is configured to send a request to shorten a duration of the waiting mode to the semiconductor wafer test apparatus, and
the semiconductor wafer test apparatus is configured to be maintained in the waiting mode for a reduced idle time in response to receipt of the request to shorten the duration of the waiting mode.
10 . A method performed by a semiconductor wafer test apparatus, the method comprising:
managing, by a test operating server, a wafer test schedule and sending a request to switch to a waiting mode or to a ready mode to the semiconductor wafer test apparatus in accordance with the wafer test schedule; and
switching the semiconductor wafer test apparatus to the waiting mode in response to receipt of the request to switch to the waiting mode from the test operating server and switching the semiconductor wafer test apparatus to the ready mode in response to receipt of the request to switch to the ready mode from the test operating server, wherein
the test operating server is configured to send the request to switch to the waiting mode when a first lot of wafers to be tested is unloaded, and send the request to switch to the ready mode before loading of a second lot of wafers to be tested.
11 . The method of claim 10 , wherein
in the waiting mode, a supply of power to first hardware boards of the semiconductor wafer test apparatus is cut off, and a power to essential devices of the semiconductor wafer test apparatus is maintained,
the essential devices include a test management processor (TMP), a main frame interface board, and second hardware boards of a tester head, and
the second hardware boards include an algorithmic pattern generator (ALPG) board and a test head interface board.
12 . The method of claim 10 , wherein
the semiconductor wafer test apparatus is further configured to switch to the waiting mode in response to receipt of the request to switch sent by the test operating server when the first lot of wafers is loaded, and is further configured to switch to the ready mode in response to receipt of the request to switch sent by the test operating server before the loading of the second lot of wafers.
13 . The method of claim 10 , wherein
the test operating server is configured to designate an idle time based on the wafer test schedule and send a request to switch to the waiting mode during the idle time, and
the semiconductor wafer test apparatus is configured to switch to the waiting mode during the idle time in response to receipt of the request to switch to the waiting mode during the idle time and is configured to automatically switch to the ready mode after a lapse of the idle time.
14 . The method of claim 13 , wherein the idle time is an amount of time required for at least one of a maintenance of the semiconductor wafer test apparatus, a replacement of a probe card, and a change of a temperature condition for a wafer test.
15 . The method of claim 14 , wherein
in response to the idle time being reduced due to a change in the wafer test schedule, the test operating server is configured send a request to shorten a duration of the waiting mode to the semiconductor wafer test apparatus, and
the semiconductor wafer test apparatus is configured to be maintained in the waiting mode for a reduced idle time in response to receipt of the request to shorten the duration of the waiting mode.
16 . The method of claim 13 , wherein an interval between a start time of unloading of the first lot of wafers and a scheduled start time of the loading of the second lot of wafers is set as the idle time in response to the interval being equal to or greater than a reference value.
17 . The method of claim 16 , wherein the reference value is an average waiting time of the semiconductor wafer test apparatus.
18 . The method of claim 13 , wherein
in response to the idle time being extended due to a change in the wafer test schedule, the test operating server is configured to send a request to extend a duration of the waiting mode to the semiconductor wafer test apparatus, and
the semiconductor wafer test apparatus is configured to be maintained in the waiting mode for an extended idle time in response to receipt of the request to extend the duration of the waiting mode.